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W9725G6KB25A Datasheet(HTML) 45 Page - Winbond

Part No. W9725G6KB25A
Description  DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
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Maker  WINBOND [Winbond]
Homepage  http://www.winbond.com
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W9725G6KB25A Datasheet(HTML) 45 Page - Winbond

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W9725G6KB
Publication Release Date: Sep. 03, 2012
- 45 -
Revision A03
10.11.2 AC Characteristics and Operating Condition for -25/25I/25A/25K/-3 speed grade
Notes: 1-3 and 45-47 apply to the entire table
SYM.
SPEED GRADE
DDR2-800
(-25/25I/25A/25K)
DDR2-667
(-3)
UNITS
25 NOTES
Bin(CL-tRCD-tRP)
5-5-5/6-6-6
5-5-5
PARAMETER
MIN.
MAX.
MIN.
MAX.
tRCD
Active to Read/Write Command Delay Time
12.5
15
nS
23
tRP
Precharge to Active Command Period
12.5
15
nS
23
tRC
Active to Ref/Active Command Period
57.5
60
nS
23
tRAS
Active to Precharge Command Period
45
70000
45
70000
nS
4,23
tRFC
Auto Refresh to Active/Auto Refresh command
period
75
75
nS
5
tREFI
Average periodic
refresh Interval
-40°C
TCASE 85°C*
7.8
μS
5
0°C
< TCASE
85°C
7.8
7.8
μS
5
85°C
< TCASE
95°C
3.9
3.9
μS
5,6
95°C
< TCASE
105°C*
3.9
μS
5,6
tCCD
CAS to CAS command delay
2
2
nCK
tCK(avg) Average clock period
tCK(avg) @ CL=3
5
8
5
8
nS
30,31
tCK(avg) @ CL=4
3.75
8
3.75
8
nS
30,31
tCK(avg) @ CL=5
2.5
8
3
8
nS
30,31
tCK(avg) @ CL=6
2.5
8
nS
30,31
tCH(avg) Average clock high pulse width
0.48
0.52
0.48
0.52
tCK(avg)
30,31
tCL(avg) Average clock low pulse width
0.48
0.52
0.48
0.52
tCK(avg)
30,31
tAC
DQ output access time from CLK/
CLK
-400
400
-450
450
pS
35
tDQSCK DQS output access time from CLK / CLK
-350
350
-400
400
pS
35
tDQSQ
DQS-DQ skew for DQS & associated DQ signals
200
240
pS
13
tCKE
CKE minimum high and low pulse width
3
3
nCK
7
tRRD
Active to active command period for 1KB page size
7.5
7.5
nS
8,23
tFAW
Four Activate Window for 1KB page size
35
37.5
nS
23
tWR
Write recovery time
15
15
nS
23
tDAL
Auto-precharge write recovery + precharge time
WR + tnRP
WR + tnRP
nCK
24
tWTR
Internal Write to Read command delay
7.5
7.5
nS
9,23
tRTP
Internal Read to Precharge command delay
7.5
7.5
nS
4,23
tIS (base) Address and control input setup time
175
200
pS
10,26,
40,42,43
tIH (base) Address and control input hold time
250
275
pS
11,26,
40,42,43
tIS (ref)
Address and control input setup time
375
400
pS
10,26,
40,42,43
tIH (ref)
Address and control input hold time
375
400
pS
11,26,
40,42,43
tIPW
Address and control input pulse width for each input
0.6
0.6
tCK(avg)
tDQSS
DQS latching rising transitions to associated clock
edges
-0.25
0.25
-0.25
0.25
tCK(avg)
28
tDSS
DQS falling edge to CLK setup time
0.2
0.2
tCK(avg)
28
tDSH
DQS falling edge hold time from CLK
0.2
0.2
tCK(avg)
28
tDQSH
DQS input high pulse width
0.35
0.35
tCK(avg)
tDQSL
DQS input low pulse width
0.35
0.35
tCK(avg)
* -40°C
≤ TCASE ≤ 85°C is for 25I/25A/25K grade only, 95°C < TCASE ≤ 105°C is for 25K grade only.


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