Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

W9725G6KB25A Datasheet(PDF) 23 Page - Winbond

Part # W9725G6KB25A
Description  DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
Download  87 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W9725G6KB25A Datasheet(HTML) 23 Page - Winbond

Back Button W9725G6KB25A Datasheet HTML 19Page - Winbond W9725G6KB25A Datasheet HTML 20Page - Winbond W9725G6KB25A Datasheet HTML 21Page - Winbond W9725G6KB25A Datasheet HTML 22Page - Winbond W9725G6KB25A Datasheet HTML 23Page - Winbond W9725G6KB25A Datasheet HTML 24Page - Winbond W9725G6KB25A Datasheet HTML 25Page - Winbond W9725G6KB25A Datasheet HTML 26Page - Winbond W9725G6KB25A Datasheet HTML 27Page - Winbond Next Button
Zoom Inzoom in Zoom Outzoom out
 23 / 87 page
background image
W9725G6KB
Publication Release Date: Sep. 03, 2012
- 23 -
Revision A03
8.3.10 No-Operation Command
( CS = "L", RAS = "H", CAS = "H", WE = "H", CKE, BA0, BA1, A0 to A12 = Don‟t Care)
The No-Operation command simply performs no operation (same command as Device Deselect).
8.3.11 Device Deselect Command
( CS = "H", RAS , CAS , WE , CKE, BA0, BA1, A0 to A12 = Don‟t Care)
The Device Deselect command disables the command decoder so that the RAS , CAS , WE and
Address inputs are ignored. This command is similar to the No-Operation command.
8.4
Read and Write access modes
The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will
initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is
strictly restricted to specific segments of the page length.
The 4 Mbit x 16 I/O x 4 Bank chip has a page length of 512 bits (defined by CA0 to CA8)
*. The page
length of 512 is divided into 128 or 64 uniquely addressable boundary segments depending on burst
length, 128 for 4 bit burst, 64 for 8 bit burst respectively. A 4-bit or 8-bit burst operation will occur
entirely within one of the 128 or 64 groups beginning with the column address supplied to the device
during the Read or Write Command (CA0 to CA8). The second, third and fourth access will also occur
within this group segment. However, the burst order is a function of the starting address, and the burst
sequence.
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting.
However, in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one
reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundary
respectively. The minimum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for
read or write cycles.
Note: Page length is a function of I/O organization and column addressing
4M bits × 16 organization (CA0 to CA8); Page Length = 512 bits
8.4.1
Posted CAS
Posted CAS operation is supported to make command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write
command to be issued immediately after the RAS bank activate command (or any time during the
RAS - CAS -delay time, tRCD, period). The command is held for the time of the Additive Latency (AL)
before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the
CAS Latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin,
then AL (greater than 0) must be written into the EMR (1). The Write Latency (WL) is always defined
as RL -1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS
Latency (RL = AL + CL). Read or Write operations using AL allow seamless bursts. (Example timing
waveforms refer to 11.10 and 11.11 seamless burst read/write operation diagram in Chapter 11)
8.4.1.1
Examples of posted CAS operation
Examples of a read followed by a write to the same bank where AL = 2 and where AL = 0 are shown
in Figures 14 and 15, respectively.


Similar Part No. - W9725G6KB25A

ManufacturerPart #DatasheetDescription
logo
Winbond
W9725G6KB25I-TR WINBOND-W9725G6KB25I-TR Datasheet
1Mb / 87P
   4M X 4 BANKS X 16 BIT DDR2 SDRAM
More results

Similar Description - W9725G6KB25A

ManufacturerPart #DatasheetDescription
logo
Winbond
W971GG6JB25I WINBOND-W971GG6JB25I Datasheet
1Mb / 87P
   DLL aligns DQ and DQS transitions with clock, Auto Refresh and Self Refresh modes, Write Data Mask
logo
Alliance Semiconductor ...
AS4C4M32D1A-5BIN ALSC-AS4C4M32D1A-5BIN Datasheet
2Mb / 64P
   DLL aligns DQ and DQS transitions
logo
ATMEL Corporation
AT24C16A ATMEL-AT24C16A_14 Datasheet
257Kb / 20P
   Write Protect Pin for Hardware Data Protection
AT24C32A ATMEL-AT24C32A_14 Datasheet
228Kb / 18P
   Write Protect Pin for Hardware Data Protection
AT24HC04B ATMEL-AT24HC04B_14 Datasheet
706Kb / 18P
   Write Protect Pin for Hardware Data Protection
AT24C04AN-10SU-1.8 ATMEL-AT24C04AN-10SU-1.8 Datasheet
194Kb / 21P
   Write Protect Pin for Hardware Data Protection
logo
Integrated Silicon Solu...
IS43LR16800G ISSI-IS43LR16800G Datasheet
1Mb / 43P
   DM for write masking only
logo
ATMEL Corporation
AT24C02A ATMEL-AT24C02A_14 Datasheet
563Kb / 16P
   Write Protect Pin for Hardware Data Protection
AT24C128 ATMEL-AT24C128_14 Datasheet
149Kb / 17P
   Write Protect Pin for Hardware and Software Data Protection
AT24C256 ATMEL-AT24C256_14 Datasheet
149Kb / 17P
   Write Protect Pin for Hardware and Software Data Protection
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com