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W9725G6KB25A Datasheet(PDF) 27 Page - Winbond |
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W9725G6KB25A Datasheet(HTML) 27 Page - Winbond |
27 / 87 page W9725G6KB Publication Release Date: Sep. 03, 2012 - 27 - Revision A03 8.6 Precharge operation The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 are used to define which bank to precharge when the command is issued. Table 4 – Bank selection for precharge by address bits A10 BA1 BA0 Precharge Bank(s) LOW LOW LOW Bank 0 only LOW LOW HIGH Bank 1 only LOW HIGH LOW Bank 2 only LOW HIGH HIGH Bank 3 only HIGH Don ‟t Care Don ‟t Care All Banks 8.6.1 Burst read operation followed by precharge Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max(RTP, 2) - 2 clks For the earliest possible precharge, the precharge command may be issued on the rising edge which is “Additive Latency (AL) + BL/2 + max(RTP, 2) - 2 clocks” after a Read command. A new bank active (command) may be issued to the same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied. The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command. (Example timing waveforms refer to 11.15 to 11.19 Burst read operation followed by precharge diagram in Chapter 11) 8.6.2 Burst write operation followed by precharge Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay. (Example timing waveforms refer to 11.20 to 11.21 Burst write operation followed by precharge diagram in Chapter 11) 8.7 Auto-precharge operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command or the Auto-precharge function. When a Read or a Write command is given to the DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is LOW when the READ or WRITE command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is HIGH when the Read or Write command is issued, then the Auto-precharge function is engaged. During Auto-precharge, a Read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is CAS Latency (CL) clock cycles before the end of the read burst. |
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