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W25Q128FVEIG Datasheet(HTML) 49 Page - Winbond

Part No. W25Q128FVEIG
Description  SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
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Maker  WINBOND [Winbond]
Homepage  http://www.winbond.com
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W25Q128FVEIG Datasheet(HTML) 49 Page - Winbond

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W25Q128FV
Publication Release Date: October 01, 2012
- 48 -
Revision D
8.2.15 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by
driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and
at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction
while data is being sent to the device. The Page Program instruction sequence is shown in Figure 29.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining
page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a
partial page) can be programmed without having any effect on other bytes within the same page. One
condition to perform a partial page program is that the number of clocks cannot exceed the remaining
page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the
page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven
high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register
is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by
the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
CLK
DI
(IO
0)
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (02h)
8
9
10
28
29
30
39
24-Bit Address
23
22
21
3
2
1
*
/CS
CLK
DI
(IO
0)
40
41
42
43
44
45
46
47
Data Byte 2
48
49
50
52
53
54
55
7
6
5
4
3
2
1
0
51
39
0
31
0
32
33
34
35
36
37
38
Data Byte 1
7
6
5
4
3
2
1
*
Mode 0
Mode 3
Data Byte 3
0
Data Byte 256
*
7
6
5
4
3
2
1
0
*
7
6
5
4
3
2
1
0
*
= MSB
*
Figure 29a. Page Program Instruction (SPI Mode)


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