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W25Q128FVEIG Datasheet(HTML) 63 Page - Winbond

Part No. W25Q128FVEIG
Description  SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
Download  97 Pages
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Maker  WINBOND [Winbond]
Homepage  http://www.winbond.com
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W25Q128FVEIG Datasheet(HTML) 63 Page - Winbond

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W25Q128FV
Publication Release Date: October 01, 2012
- 62 -
Revision D
8.2.26 Read Manufacturer / Device ID Dual I/O (92h)
The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID
at 2x speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by a
24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock.
After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on
the falling edge of CLK with most significant bits (MSB) first as shown in Figure 40. The Device ID values
for the W25Q128FV are listed in Manufacturer and Device Identification table. If the 24-bit address is
initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The
Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction
is completed by driving /CS high.
/CS
CLK
DI
(IO
0)
DO
(IO
1)
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (92h)
High Impedance
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
7
5
3
1
**
6
4
2
0
7
5
3
1
6
4
2
0
7
5
3
1
6
4
2
0
7
5
3
1
6
4
2
0
23
**
A23-16
A15-8
A7-0 (00h)
M7-0
/CS
CLK
DI
(IO
0)
DO
(IO
1)
24
25
26
27
28
29
30
31
32
33
34
36
37
38
35
23
0
Mode 0
Mode 3
7
5
3
1
6
4
2
0
7
5
3
1
6
4
2
0
7
5
3
1
6
4
2
0
7
5
3
6
4
2
1
0
1
MFR ID
Device ID
MFR ID
(repeat)
Device ID
IOs switch from
Input to Output
(repeat)
**
**
= MSB
*
Figure 40. Read Manufacturer / Device ID Dual I/O Instruction (SPI Mode only)
Note:
The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction.


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