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ADP5052ACPZ-R7 Datasheet(HTML) 20 Page - Analog Devices

Part No. ADP5052ACPZ-R7
Description  5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP5052ACPZ-R7 Datasheet(HTML) 20 Page - Analog Devices

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ADP5052
Data Sheet
Rev. 0 | Page 20 of 40
The SS12 pin can be used to program the soft start time and
parallel operation for Channel 1 and Channel 2. The SS34 pin
can be used to program the soft start time for Channel 3 and
Channel 4. Table 8 provides the values of the resistors needed to
set the soft start time.
Table 8. Soft Start Time Set by the SS12 and SS34 Pins
Soft Start Time
Soft Start Time
RTOP (kΩ) RBOT (kΩ) Channel 1 Channel 2 Channel 3 Channel 4
0
N/A
2 ms
2 ms
2 ms
2 ms
100
600
2 ms
Parallel
2 ms
4 ms
200
500
2 ms
8 ms
2 ms
8 ms
300
400
4 ms
2 ms
4 ms
2 ms
400
300
4 ms
4 ms
4 ms
4 ms
500
200
8 ms
2 ms
4 ms
8 ms
600
100
8 ms
Parallel
8 ms
2 ms
N/A
0
8 ms
8 ms
8 ms
8 ms
PARALLEL OPERATION
The ADP5052 supports two-phase parallel operation of Channel 1
and Channel 2 to provide a single output with up to 8 A of current.
To configure Channel 1 and Channel 2 as a two-phase single output
in parallel operation, do the following (see Figure 44):
Use the SS12 pin to select parallel operation as specified
in Table 8.
Leave the COMP2 pin open.
Use the FB1 pin to set the output voltage.
Connect the FB2 pin to ground (FB2 is ignored).
Connect the EN2 pin to ground (EN2 is ignored).
CHANNEL 1
BUCK
REGULATOR
(4A)
CHANNEL 2
BUCK
REGULATOR
(4A)
FB1
PVIN1
VOUT
(UP TO 8A)
VIN
EN1
EN2
COMP1
SS12
SW1
L1
FB2
SW2
L2
PVIN2
COMP2
VREG
Figure 44. Parallel Operation for Channel 1 and Channel 2
When Channel 1 and Channel 2 are operated in the parallel
configuration, configure the channels as follows:
Set the input voltages and current-limit settings for
Channel 1 and Channel 2 to the same values.
Operate both channels in forced PWM mode.
Current balance in parallel configuration is well regulated by
the internal control loop. Figure 45 shows the typical current
balance matching in the parallel output configuration.
0
1
2
3
4
5
6
0
2
4
6
8
10
TOTAL OUTPUT LOAD (A)
CH1
CH2
IDEAL
Figure 45. Current Balance in Parallel Output Configuration,
VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode
STARTUP WITH PRECHARGED OUTPUT
The buck regulators in the ADP5052 include a precharged
start-up feature to protect the low-side FETs from damage
during startup. If the output voltage is precharged before the
regulator is turned on, the regulator prevents reverse inductor
current—which discharges the output capacitor—until the
internal soft start reference voltage exceeds the precharged
voltage on the feedback (FBx) pin.
CURRENT-LIMIT PROTECTION
The buck regulators in the ADP5052 include peak current-limit
protection circuitry to limit the amount of positive current flowing
through the high-side MOSFET. The peak current limit on the
power switch limits the amount of current that can flow from the
input to the output. The programmable current-limit threshold
feature allows for the use of small size inductors for low current
applications.
To configure the current-limit threshold for Channel 1, connect
a resistor from the DL1 pin to ground; to configure the current-
limit threshold for Channel 2, connect another resistor from the
DL2 pin to ground. Table 9 lists the peak current-limit threshold
settings for Channel 1 and Channel 2.
Table 9. Peak Current-Limit Threshold Settings
for Channel 1 and Channel 2
RILIM1 or RILIM2
Typical Peak Current-Limit Threshold
Floating
4.4 A
47 kΩ
2.63 A
22 kΩ
6.44 A
The buck regulators in the ADP5052 include negative current-
limit protection circuitry to limit certain amounts of negative
current flowing through the low-side MOSFET.


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