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ADP5052ACPZR7 Datasheet(HTML) 23 Page  Analog Devices 

ADP5052ACPZR7 Datasheet(HTML) 23 Page  Analog Devices 
Data Sheet ADP5052 Rev. 0  Page 23 of 40 APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL The ADP5052 is supported by the ADIsimPower™ design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic and bill of materials and to calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and part count while taking into consideration the operating conditions and limitations of the IC and all real external components. The ADIsimPower tool can be found at www.analog.com/ADIsimPower; the user can request an unpopulated board through the tool. PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE The output voltage of the ADP5052 is externally set by a resistive voltage divider from the output voltage to the FBx pin. To limit the degradation of the output voltage accuracy due to feedback bias current, ensure that the bottom resistor in the divider is not too large—a value of less than 50 kΩ is recommended. The equation for the output voltage setting is VOUT = VREF × (1 + (RTOP/RBOT)) where: VOUT is the output voltage. VREF is the feedback reference voltage: 0.8 V for Channel 1 to Channel 4 and 0.5 V for Channel 5. RTOP is the feedback resistor from VOUT to FB. RBOT is the feedback resistor from FB to ground. No resistor divider is required in the fixed output options. If a different fixed output voltage is required, contact your local Analog Devices sales or distribution representative. VOLTAGE CONVERSION LIMITATIONS For a given input voltage, upper and lower limitations on the output voltage exist due to the minimum on time and the minimum off time. The minimum output voltage for a given input voltage and switching frequency is limited by the minimum on time. The minimum on time for Channel 1 and Channel 2 is 117 ns (typical); the minimum on time for Channel 3 and Channel 4 is 90 ns (typical). The minimum on time increases at higher junction temperatures. Note that in forced PWM mode, Channel 1 and Channel 2 can potentially exceed the nominal output voltage when the mini mum on time limit is exceeded. Careful switching frequency selection is required to avoid this problem. The minimum output voltage in continuous conduction mode (CCM) for a given input voltage and switching frequency can be calculated using the following equation: VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON1 − RDSON2) × IOUT_MIN × tMIN_ON × fSW − (RDSON2 + RL) × IOUT_MIN (1) where: VOUT_MIN is the minimum output voltage. tMIN_ON is the minimum on time. fSW is the switching frequency. RDSON1 is the on resistance of the highside MOSFET. RDSON2 is the on resistance of the lowside MOSFET. IOUT_MIN is the minimum output current. RL is the resistance of the output inductor. The maximum output voltage for a given input voltage and switching frequency is limited by the minimum off time and the maximum duty cycle. Note that the frequency foldback feature helps to increase the effective maximum duty cycle by lowering the switching frequency, thereby decreasing the dropout voltage between the input and output voltages (see the Frequency Foldback section). The maximum output voltage for a given input voltage and switch ing frequency can be calculated using the following equation: VOUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON1 − RDSON2) × IOUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON2 + RL) × IOUT_MAX (2) where: VOUT_MAX is the maximum output voltage. tMIN_OFF is the minimum off time. fSW is the switching frequency. RDSON1 is the on resistance of the highside MOSFET. RDSON2 is the on resistance of the lowside MOSFET. IOUT_MAX is the maximum output current. RL is the resistance of the output inductor. As shown in Equation 1 and Equation 2, reducing the switching frequency eases the minimum on time and off time limitations. CURRENTLIMIT SETTING The ADP5052 has three selectable currentlimit thresholds for Channel 1 and Channel 2. Make sure that the selected current limit value is larger than the peak current of the inductor, IPEAK. See Table 9 for the currentlimit configuration for Channel 1 and Channel 2. 
