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ADP5052ACPZ-R7 Datasheet(HTML) 26 Page - Analog Devices

Part No. ADP5052ACPZ-R7
Description  5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP5052ACPZ-R7 Datasheet(HTML) 26 Page - Analog Devices

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ADP5052
Data Sheet
Rev. 0 | Page 26 of 40
COMPENSATION COMPONENTS DESIGN
For the peak current-mode control architecture, the power
stage can be simplified as a voltage controlled current source
that supplies current to the output capacitor and load resistor.
The simplified loop is composed of one domain pole and a zero
contributed by the output capacitor ESR. The control-to-output
transfer function is shown in the following equations:
×
π
×
+
×
π
×
+
×
×
=
=
p
z
VI
COMP
OUT
vd
f
s
f
s
R
A
s
V
s
V
s
G
2
1
2
1
)
(
)
(
)
(
OUT
ESR
z
C
R
f
×
×
π
×
=
2
1
(
)
OUT
ESR
p
C
R
R
f
×
+
×
π
×
=
2
1
where:
AVI = 10 A/V for Channel 1 or Channel 2, and 3.33 A/V for
Channel 3 or Channel 4.
R is the load resistance.
RESR is the equivalent series resistance of the output capacitor.
COUT is the output capacitance.
The ADP5052 uses a transconductance amplifier as the error
amplifier to compensate the system. Figure 49 shows the sim-
plified peak current-mode control small signal circuit.
RESR
R
+
g
m
RC
CCP
COUT
CC
RTOP
RBOT
+
AVI
VOUT
VCOMP
VOUT
Figure 49. Simplified Peak Current-Mode Control Small Signal Circuit
The compensation components, RC and CC, contribute a zero;
RC and the optional CCP contribute an optional pole.
The closed-loop transfer equation is as follows:
)
(
1
1
)
(
s
G
s
C
C
C
C
R
s
s
C
R
C
C
g
R
R
R
s
T
vd
CP
C
CP
C
C
C
C
CP
C
m
TOP
BOT
BOT
V
×
×
+
×
×
+
×
×
×
+
×
+
×
+
=
The following guidelines show how to select the compensation
components—RC, CC, and CCP—for ceramic output capacitor
applications.
1. Determine the cross frequency (fC). Generally, fC is
between fSW/12 and fSW/6.
2. Calculate RC using the following equation:
VI
m
C
OUT
OUT
C
A
g
f
C
V
R
×
×
×
×
×
π
×
=
V
8
.
0
2
3. Place the compensation zero at the domain pole (fP).
Calculate CC using the following equation:
(
)
C
OUT
ESR
C
R
C
R
R
C
×
+
=
4. CCP is optional. It can be used to cancel the zero caused
by the ESR of the output capacitor. Calculate CCP using
the following equation:
C
OUT
ESR
CP
R
C
R
C
×
=
POWER DISSIPATION
The total power dissipation in the ADP5052 simplifies to
PD = PBUCK1 + PBUCK2 + PBUCK3 + PBUCK4 + PLDO
Buck Regulator Power Dissipation
The power dissipation (PLOSS) for each buck regulator includes
power switch conduction losses (PCOND), switching losses (PSW),
and transition losses (PTRAN). Other sources of power dissipation
exist, but these sources are generally less significant at the high
output currents of the application thermal limit.
Use the following equation to estimate the power dissipation of
the buck regulator:
PLOSS = PCOND + PSW + PTRAN
Power Switch Conduction Loss (PCOND)
Power switch conduction losses are caused by the flow of output
current through both the high-side and low-side power switches,
each of which has its own internal on resistance (RDSON).
Use the following equation to estimate the power switch
conduction loss:
PCOND = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT2
where:
RDSON_HS is the on resistance of the high-side MOSFET.
RDSON_LS is the on resistance of the low-side MOSFET.
D is the duty cycle (D = VOUT/VIN).


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