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ADP5052ACPZ-R7 Datasheet(HTML) 27 Page - Analog Devices

Part No. ADP5052ACPZ-R7
Description  5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP5052ACPZ-R7 Datasheet(HTML) 27 Page - Analog Devices

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Data Sheet
ADP5052
Rev. 0 | Page 27 of 40
Switching Loss (PSW)
Switching losses are associated with the current drawn by the
driver to turn the power devices on and off at the switching
frequency. Each time a power device gate is turned on or off,
the driver transfers a charge from the input supply to the gate,
and then from the gate to ground. Use the following equation
to estimate the switching loss:
PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW
where:
CGATE_HS is the gate capacitance of the high-side MOSFET.
CGATE_LS is the gate capacitance of the low-side MOSFET.
fSW is the switching frequency.
Transition Loss (PTRAN)
Transition losses occur because the high-side MOSFET cannot
turn on or off instantaneously. During a switch node transition,
the MOSFET provides all the inductor current. The source-to-
drain voltage of the MOSFET is half the input voltage, resulting
in power loss. Transition losses increase with both load and input
voltage and occur twice for each switching cycle. Use the following
equation to estimate the transition loss:
PTRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW
where:
tR is the rise time of the switch node.
tF is the fall time of the switch node.
Thermal Shutdown
Channel 1 and Channel 2 store the value of the inductor current
only during the on time of the internal high-side MOSFET.
Therefore, a small amount of power (as well as a small amount
of input rms current) is dissipated inside the ADP5052, which
reduces thermal constraints.
However, when Channel 1 and Channel 2 are operating under
maximum load with high ambient temperature and high duty
cycle, the input rms current can become very large and cause
the junction temperature to exceed the maximum junction tem-
perature of 125°C. If the junction temperature exceeds 150°C,
the regulator enters thermal shutdown and recovers when the
junction temperature falls below 135°C.
LDO Regulator Power Dissipation
The power dissipation of the LDO regulator is given by the
following equation:
PLDO = [(VIN − VOUT) × IOUT] + (VIN × IGND)
where:
VIN and VOUT are the input and output voltages of the LDO
regulator.
IOUT is the load current of the LDO regulator.
IGND is the ground current of the LDO regulator.
Power dissipation due to the ground current is small in the
ADP5052 and can be ignored.
JUNCTION TEMPERATURE
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to power dissipation, as shown in the following
equation:
TJ = TA + TR
where:
TJ is the junction temperature.
TA is the ambient temperature.
TR is the rise in temperature of the package due to power
dissipation.
The rise in temperature of the package is directly proportional
to the power dissipation in the package. The proportionality
constant for this relationship is the thermal resistance from the
junction of the die to the ambient temperature, as shown in the
following equation:
TR = θJA × PD
where:
TR is the rise in temperature of the package.
θJA is the thermal resistance from the junction of the die to the
ambient temperature of the package (see Table 5).
PD is the power dissipation in the package.
An important factor to consider is that the thermal resistance
value is based on a 4-layer, 4 inch × 3 inch PCB with 2.5 oz. of
copper, as specified in the JEDEC standard, whereas real-world
applications may use PCBs with different dimensions and a
different number of layers.
It is important to maximize the amount of copper used to remove
heat from the device. Copper exposed to air dissipates heat better
than copper used in the inner layers. Connect the exposed pad
to the ground plane with several vias.


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