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DAC1653Q Datasheet(HTML) 2 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
Download  101 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 2 Page - Integrated Device Technology

 
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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
2 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
Multiple Device Synchronization (MDS) enables multiple DAC channels to be sample
synchronous and phase coherent to within one DAC clock period. MDS is ideal for LTE
and LTE-A MIMO transceiver applications.
The DAC165xQ includes an internal regulation to adjust the full-scale output current. The
internal regulator adjusts the full-scale output current between 8.1 mA and 34 mA. The
device is available in a HLA72 package (10 mm
 10 mm). It is supported by customer
demo boards that are supplied with or without FPGA logic devices.
2. Features and benefits
quad channel 16-bit resolution
SFDRRBW = 85 dBc typical
(fs = 1.47456 Gsps; interpolation 2;
bandwidth = 250 MHz; fout = 150 MHz)
1.50 GSps maximum output update rate NSD =
162 dBm/Hz typical
(fo = 20 MHz)
JEDEC JESD204B device subclass I
compatible: SYSREF based
deterministic and repeatable interface
latency
IMD3 = 85 dBc typical
(fs = 1.47456 Gsps; interpolation 2;
fo1 = 152 MHz; fo2 = 153 MHz)
Multiple Device Synchronization (MDS)
enables multiple DAC channels to be
sample synchronous and phase
coherent to within one DAC clock period
one carrier ACLR = 77 dB typical
(fs = 1.47456 Gsps; fNCO = 230 MHz)
8 configurable JESD204B serial input
lanes running up to 10 Gbps with
embedded termination and
programmable equalization gain
RF enable/disable pin and RF automatic
mute. The RF enable feature is available
via one of the IO pins
750 Msps maximum baseband input
data rate
very low noise bypassable integrated
Phase-Locked Loop (PLL); no external
capacitors
SPI interface (3-wire or 4-wire mode) for
control setting and status monitoring
clock divider by 2, 4, 6 or 8 available at
the input of the clock path
differential scalable output current from
8.1 mA to 34 mA
group delay compensation
two embedded NCOs with 40-bit
programmable frequency and 16-bit
phase adjustment
power-down mode control
embedded complex (IQ) digital
modulator
on-chip 0.7 V reference
1.2 V and 2.5 V or 3.3 V power supplies industrial temperature range
40 C to +85 C
flexible SPI power supply (1.8 V or
1.2 V) ensuring compatibility with
on-board SPI bus
HLA72 package (10 mm
 10 mm)
flexible differential signals (SYNC)
power supply (1.8 V or 1.2 V) ensuring
compatibility with on-board devices


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