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DAC1653Q Datasheet(HTML) 26 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 26 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
26 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
11.2 Device operation
The DAC165xQ provides a lot of flexibility in its way of working through its SPI registers.
The SPI registers are divided in blocks of registers. Each block is associated with some
global functions which are described below.
Fig 7.
SPI register blocks partition: DAC A/B
power
on/off
sleep
CLOCK DISTRIBUTION
CLOCK GENERATION
DIRECT MODE/
DIVIDE BY 2 MODE
DACA
DACB
VIN_AB_P3
VIN_AB_N3
SYNCB_AB_P
SYNCB_AB_N
VIN_AB_P2
VIN_AB_N2
VIN_AB_P1
VIN_AB_N1
VIN_AB_P0
L0
Eq
L1
L2
L3
VIN_AB_N0
AUTO CAL
EQUALIZER
CONTROL
BLOCK 0040h: MAIN CONTROLS
MONITORING
CONTROL
MDS Managment
SYSREF
EAST
SYSREF
WEST
INTERRUPTS
BLOCK 0120h/0140h: JESD204 READ CONFIGURATION
DID, BID, ADJ_CNT, ADJ_DIR, PH_ADJ, SCR, L,
F, K, M, N, N, SBCLSS_VS, S, HD, CF,
JESD_VS, RES1, RES2, FCHK
BLOCK 0160h: RX PHY
BLOCK 00C0h: RX DLP
BLOCK 0060h: INTERFACE DAC DSP
BLOCK 0020h: DUAL DAC CORE
BLOCK 0180h:
RX PHY MONITORING
Auto Equalizer
CDR
Termination
Calibration
Lanes Lock
ILA monitoring
Error detection
Simple BER
Flags counter
BLOCK 00E0h:
RX DLP MONITORING
BLOCK 00A0h:
MUTIPLES DEVICES SYNCHRONIZATION/INTERRUPTS
Eq
Eq
Eq
Sync Mgmt


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