DAC1653Q datasheet(27/101 Pages) IDT

Part #	DAC1653Q

Description	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50

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Manufacturer	IDT [Integrated Device Technology]

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DAC1653Q/DAC1658Q

Advance data sheet

Rev. 1.03 — 13 May 2013

27 of 101

Integrated Device Technology

DAC1653Q/DAC1658Q

Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps

11.2.1 SPI configuration block

This block of registers specifies how the SPI controller and the identification of the chip

work.

11.2.1.1 Protocol description

The DAC165xQ serial interface is a synchronous serial communication port allowing easy

interfacing with many industry microprocessors. It provides access to the registers that

define the operating modes of the chip in both Write mode and Read mode. The reference

voltage of the interface is VDDD(IO). Depending on the power supply level of the SPI master

device, it can be set to either 1.2 V or 1.8 V.

This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire

type (SDIO and SDO as unidirectional pins, input and output ports, respectively). In both

configurations, SCLK acts as the serial clock and SCS_N acts as the serial chip select.

The DAC165xQ SPI-interface is a slave-device. Multiple slave-devices can be attached to

the same master interface as long as each device has its own serial chip select signal

(SCS_N).

Fig 8.

SPI register blocks partition: DAC C/D

power

on/off

sleep

CLOCK DISTRIBUTION

CLOCK GENERATION

DIRECT MODE/

DIVIDE BY 2 MODE

DACC

DACD

VIN_CD_P3

VIN_CD_N3

SYNCB_CD_P

SYNCB_CD_N

VIN_CD_P2

VIN_CD_N2

VIN_CD_P1

VIN_CD_N1

VIN_CD_P0

L0

Eq

L1

L2

L3

VIN_CD_N0

MDS Managment

SYSREF

EAST

SYSREF

WEST

INTERRUPTS

BLOCK 0320h/0340h: JESD204 READ CONFIGURATION

DID, BID, ADJ_CNT, ADJ_DIR, PH_ADJ, SCR, L,

F, K, M, N, N, SBCLSS_VS, S, HD, CF,

JESD_VS, RES1, RES2, FCHK

BLOCK 0360h: RX PHY

BLOCK 02C0h: RX DLP

BLOCK 0260h: INTERFACE DAC DSP

BLOCK 0220h: DUAL DAC CORE

BLOCK 0380h:

RX PHY MONITORING

Auto Equalizer

CDR

Termination

Calibration

Lanes Lock

ILA monitoring

Error detection

Simple BER

Flags counter

BLOCK 02E0h:

RX DLP MONITORING

BLOCK 02A0h:

MUTIPLES DEVICES SYNCHRONIZATION/INTERRUPTS

Eq

Sync Mgmt

AUTO CAL

EQUALIZER

CONTROL

BLOCK 0240h: MAIN CONTROLS

MONITORING

CONTROL

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