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DAC1653Q Datasheet(HTML) 28 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 28 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
28 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
A[14:0] indicates which register is being addressed. If a multiple transfer occurs, this
address points to the first register to be accessed.
11.2.1.2 SPI controller configuration
The 3-wire or 4-wire mode is set by bit SPI_4W of register SPI_CFG_A . The default
mode is 3-wire mode.
A software SPI reset can be called via bit SPI_RST of register SPI_CFG_A . This reset
reinitializes all SPI registers, except register SPI_CFG_A and SPI_CFG_B, to their default
settings. Reset the device to its default value at start-up time to avoid any uncontrolled
states, even if the DAC165xQ uses the Power-On Reset (POR) module. Only a hardware
reset on pin RESET_N can reset to their default values.
The SPI streaming mode is enabled by default. In this mode, the Read or Write process
carries on as long as the SCS_N signal is low. The streaming mode requires a first
address 'n' to be set at the beginning of the SPI sequence. The following data are
associated from this address in an ascending (auto-increment) or descending
(auto-decrement) mode. This ascending/descending mode is specified by bit SPI_ASC of
register SPI_CONFIG_A . Figure 10 and Figure 11 show the read back of 2 bytes data in
a 3-wire mode for the ascendant and descendant mode.
R/W indicates the mode access.
The RESET_N signal is not linked to the SPI interface but enable the reset of the registers to the default values.
Fig 9.
SPI protocol
RESET_N
SCS_N
SCLK
SDIO
SDO
(optional)
R/W
A14
A13
A4
A3
A2
A1
A0
D7
D6
D5
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Table 11.
Read mode or Write mode access description
R/W
Description
0
Write mode operation
1
Read mode operation
Fig 10. Consecutive 2-byte data readback under descending address
address N
register N value
register N - 1 value
SCS_N
SCLK
SDIO
R/W A14 A13 A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0


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