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DAC1653Q Datasheet(HTML) 29 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 29 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
29 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
The streaming mode can be disabled by setting bit SPI_SNGL of register SPI_CONFIG_B
. In this single-byte mode, only 1 byte of data can be written or read, whatever the state of
the SCS_N signal.
11.2.1.3 Double buffering and Transfer mode
Some register functions (like the NCO frequency value) are split over multiple registers. If
this is the case, the first address consists of the LSB byte and the highest address in the
MSB byte. When programming these registers sequentially, some unexpected behavior
can occur at the DAC output. it is preferable to program this set of registers
simultaneously. A double buffering feature is available on some registers allowing
sequential programming of the first buffers and transfering the values to the final register
simultaneously.
The transfer request is done by setting the TRANSFER_BIT bit of register
SPI_CONFIG_C register . The device clears this bit (autoclear) indicating to the SPI
master device that the transfer is complete.
The SPI_RBACK_BUFF bit of register SPI_CONFIG_B allows the reading back of the first
stage of buffers (in case the register is double buffered)
The following registers are double buffered:
Fig 11. Consecutive 2-byte data readback under ascending address
address N
register N value
register N + 1 value
SCS_N
SCLK
SDIO
R/W A14 A13 A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Table 12.
Double buffered registers
Address
Register
0062h/0262h/046Ah
NCO_PH_OFFSET_XY_LSB
0063h/0263h/0463h
NCO_PH_OFFSET_XY_MSB
0064h/0264h/0464h
NCO_FREQ_XY_B0
0065h/0265h/0465h
NCO_FREQ_XY_B1
0066h/0266h/0466h
NCO_FREQ_XY_B2
0067h/0267h/0467h
NCO_FREQ_XY_B3
0068h/0268h/0468h
NCO_FREQ_XY_B4
0069h/0269h/0469h
PH_CORR_XY_CTRL_0
006Ah/026Ah/046Ah
PH_CORR_XY_CTRL_1
006Bh/026Bh/046Bh
DAC_X_DGAIN_LSB
006Ch/026Ch/046Ch
DAC_X_DGAIN_MSB
006Dh/026Dh/046Dh
DAC_Y_DGAIN_LSB
006Eh/026Eh/046Eh
DAC_Y_DGAIN_MSB
006Fh/026Fh/046Fh
DAC_OUT_CTRL_XY
0070h/0270h/0470h
DAC_LVL_DET_XY
0071h/0271h/0471h
DAC_X_OFFSET_LSB
0072h/0272h/0472h
DAC_X_OFFSET_MSB


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