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DAC1653Q Datasheet(HTML) 38 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 38 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
38 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
Remark: The transfer function of this features adds some gain to the signals and some
saturation can occur with a level of distortion in the output spectrum as result. Update the
digital gain accordingly to avoid this saturation.
11.2.3.7 Minus 3dB
During normal operation, a full-scale pattern is also full-scale at the DAC output. When the
I data and the Q data approach full-scale simultaneously, saturation can occur. The Minus
3dB function (bit MINUS_3DB_XY of register DAC_OUT_CTRL_XY) can be used to
reduce the 3 dB gain in the modulator. It retains a full-scale range at the DAC output
without added interferers.
11.2.3.8 Phase correction
The IQ modulator which follows the DACs can have a phase imbalance resulting in
undesired sidebands. By adjusting the phase between the I and Q channels, the
unwanted sideband can be reduced.
Without compensation the I and Q channels have a phase difference of
 / 2 (90°). The
registers PH_CORR_XY_CTRL_0 and PH_CORR_XY_CTRL_1 ensure a phase
variation from 75.7
 to 104.3 by steps 0.0035. The two registers define a signed value
that ranges from
4096 to +4095. The equation: PH_CORR[12:0] / 16384 gives the
resulting phase compensation (in radians). The phase correction can be enabled by
register PH_CORR_EN_XY .
11.2.3.9 Digital gain
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
The IQ-modulator can have an amplitude imbalance which results in undesired
sidebands. The unwanted sideband can be reduced by adjusting the amplitude of signals
A and B. The two gains are purely digital and could be enabled by registers
DAC_X_DGAIN_EN and DAC_Y_DGAIN_EN .
The output current of DAC X depends on the digital input data and the gain factor defined
by bits DAC_X_DGAIN[11:0] of register DAC_X_DGAIN_MSB and register
DAC_X_DGAIN_LSB .
Table 17.
Inversion filter coefficients
Inversion filter
Lower
Upper
Value
H(1)
H(9)
+1
H(2)
H(8)
4
H(3)
H(7)
+13
H(4)
H(6)
51
H(5)
-
+610
I OA fs

I IOUTA_P I IOUTA_N
+
=
I OB fs

I IOUTB_P I IOUTB_N
+
=
I OB fs

I IOUTC_P I IOUTC_N
+
=
I OB fs

I IOUTD_P I IOUTD_N
+
=


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