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DAC1653Q Datasheet(HTML) 42 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 42 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
42 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
Event triggered when the signal levels exceed the LVL_DET_XY on channel X or Y.
LVL_DET_EN_XY and LVL_DET_XY must be set first .
MDS_BSY_XY:
Event triggered while the MDS process is busy aligning the DAC .
DATA_IQ_VALID_XY:
Event is triggered when DATA_INVALID is detected by the DLP
SPD_OVF_XY:
Event triggered when the Signal Power Detector (SPD) average value is exceeding
the threshold value .
IQR_ERR_XY:
Event triggered when the IQ signal is out of range .
The monitoring of these events can also be done using the interrupt process available in
the DAC165xQ . Once the interrupt is detected, the host controller (e.g. an FPGA) can
read back the events flags in registers INTR_FLAGS_0_XY and INTR_FLAGS_1_XY
and determine the actions to be taken.
Ignore events option
Set bits IGN_RT_EN_XY, IGN_MDS_BSY_XY, and IGN_DATA_V_IQ_XY of the mute
control register for the mute controller to ignore certain events.
Mute event categories
The MUTE state is entered when one of the mute events is asserted. Four categories of
mute events can be distinguished: ALARM, DATA, INCIDENT, and DIRECT .


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