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DAC1653Q Datasheet(HTML) 44 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 44 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
44 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
Priority between categories
The priority in which the auto-mute module evaluates its inputs is:
Priority 1: DIRECT
Priority 2: ALARM
Priority 3: DATA
Priority 4: INCIDENT
Mute actions
Four mute actions can be selected for each of the four previous mute event categories.
The digital data can also be reset to its default value (bits I_DC_LVL_XY and
Q_DC_LVL_XY) to avoid disturbances in the FIR filters.
Register MUTE_CTRL_1_XY :
Hard_mute + mute IQ:
The digital gains of the DACs are set to zero (within 1 DAC clock period). The digital
path is filled with the default I and Q levels.
Hold_mute + mute IQ:
The outputs of the DACs are kept to the current value (within 1 DAC clock period).
The digital path is filled with the default I and Q levels.
Remark: Bit HOLD_DATA_XY must be enabled for this action. If this bit is not set,
the overall Hold_mute + mute IQ actions are not taken into account.
Soft_mute + mute IQ:
The digital gains of the DACs are swept down to zero at the
MUTE_RATE_CTRL_0_XY value . The digital path is filled with the default I and Q
levels.
Soft_mute:
The outputs of the DACs are swept down to zero at the MUTE_RATE_CTRL_0_XY
value . The digital path is kept with the received values.
Remark: As the DC offsets are applied after the digital gain, the outputs are still
impacted by their values, even if a mute action event occurs.


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