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DAC1653Q Datasheet(HTML) 46 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 46 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
46 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
Mute wait period
The wait period time can be calculated with Equation 14:
(14)
At 1 Gsps, this gives a wait period between 8 ns and 527
s.
DEMUTE triggering
When the mute action is either a DIRECT, an INCIDENT or a DATA mute action, the
WAIT state is enabled as long as the wait period is not elapsed and the event is not
released.
When the mute action is an ALARM mute action, the WAIT state is enabled as long as the
alarm controller is not reset using bit MC_ALARM_CLR_XY .
11.2.3.11 Digital offset adjustment
When the DAC165xQ analog output is DC connected to the next stage, the digital offset
correction (bits DAC_X_OFFSET[15:0] and DAC_Y_OFFSET[15:0]) can be used to
adjust the common-mode level at the output of each DAC. Table 21 shows the variation
range of the digital offset.
Table 20.
Mute rate availability
Through ALARM_MRATE_XY, DATA_MRATE_XY, INCIDENT_MRATE_XY, and
DIRECT_MRATE_XY.
DAC clock
750 MHz
1 GHz
1.5 GHz
Period
8 (ns)
10.67
8.00
5.33
Value
Mute rate (ns)
Mute rate (ns)
Mute rate (ns)
0000
10.67
8.00
5.33
0001
21.34
16.00
10.66
0010
42.68
32.00
21.32
0011
85.36
64.00
42.64
0100
170.72
128.00
85.28
0101
341.44
256.00
170.56
0110
682.88
512.00
341.12
0111
1,365.76
1,024.00
682.24
1000
2,731.52
2,048.00
1,364.48
1001
3,642.47
2,731.00
1,819.53
1010
5,463.04
4 096.00
2,728.96
1011
7,283.61
5,461.00
3,638.39
1100
10,926.08
8,192.00
5,457.92
1101
14,557.88
10,915.00
7,272.12
1110
21,852.16
16,384.00
10,915.84
1111
43,704.32
32,768.00
21,831.68
wait period
MUTE_WAIT _PERIOD 1
+
 8DAC_CLK_PERIOD
=


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