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DAC1653Q Datasheet(HTML) 48 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 48 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
48 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
11.2.4.2 Signal Power Detector (SPD)
The Signal Power Detector (SPD) takes the 7 MSBs of the I and Q signal to determine the
IQ power of an IQ-pair. Averaging is done over the programmable number (26, 27 to 221)
of IQ-pairs using the SPD_WIN_LENGTH register . If the SPD_AVG bit exceeds the
16-bits threshold value, the SPD overflow (SPD_OVF) flag becomes active and can
invoke a mute action depending on the mute control settings.
The SPD can have a large response time because of the samples average based
algorithm. This must be taken into account at system level.
11.2.4.3 IQ Range (IQR)
Table 22.
Level detector values
LVL_DET[7:0]
Peak excursion
from
full-scale / 2
Code output range
(binary offset)
dBFS value
10log(peak excursion x 2 / 65536)
00h
0
32768
NaN
...
...
...
19h
3200
32568 to 35968
10.1 dBFS
...
...
...
80h
16384
16384 to 49152
3 dBFS
...
...
...
CBh
25984
6784 to 58752
-1 dBFS
...
...
...
FFh
32768
0 to 65536
0 dBFS
Fig 24. Signal power detector
7 MSBs of I
7 MSBs of Q
I
2
+ Q
2
IQ power
SPD_WINLENGTH
AVERAGING
SPD_AVG
SPD_THRESHOLD
SPD_OVF
to the
auto-mute
module
Fig 25. IQ range
OR
I
Q
IQR_THRESHOLD
IQR_ERR
to the
auto-mute
module
RANGE DETECTOR
RANGE DETECTOR


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