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DAC1653Q Datasheet(HTML) 49 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 49 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
49 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
The IQ range detector checks if the I and Q signal values are within the range specified by
register IQR_THRESHOLD compared to the center value (= 0 if the data are in 2
complement's representation or 32768 if the data are in binary offset representation):
IQR_THRESHOLD < I  center value < +IQR_THRESHOLD
IQR_THRESHOLD < Q  center value < +IQR_THRESHOLD
11.2.5 Analog core of the dual DAC
This section refers to the analog configuration required to set up the dual DAC core. The
clock and output stages are described as well as the internal registers
(Block 0020h; see Figure 26 ) used to configure the clock tree inside the chip.
11.2.5.1 Clocks
The DAC165xQ requires one single differential clock (CLKIN_P, CLKIN_N) for the whole
device (including the digital data path, the quad DAC core and the JESD204B interface).
During the reset phase (RESET_N asserted), the input clock must be stable and running,
ensuring a proper reset of the complete device.
Clock input external configuration
The DAC165xQ incorporates one differential clock input, CLKIN_N/CLKIN_P, with
embedded 100
 differential resistor. The clock input can be LVDS but it can also be
interfaced with CML.
Block 0020h = DAC A/B
Block 0220h = DAC C/D
Block 0420h = All DACs
Fig 26. DAC core overview
BLOCK 0020h/0220h/0420h: DAC CORE
CLOCK DIVIDER
DCLK
DCLK_MON_RST_XY
DCLK_MON_XY
WCLK_DIV_BYP_XY
WCLK_DIV_SEL_XY
/ 2, / 3, / 4, / 6, / 8
/ 12, / 16, / 24
WCLK
WCLK_PON_XY
CLK_DIV_BYP
CLKIN_P
CLKIN_N
DAC X
DAC_X_AGAIN
DAC_X_AGAIN_PON
DAC_X_AUX_PON
DAC_X_AUX
DAC_Y_AUX__PON
DAC_Y_AUX
DAC_Y_AGAIN_PON
DAC_Y_AGAIN
AUX.
DAC
DAC Y
AUX.
DAC


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