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DAC1653Q Datasheet(HTML) 50 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 50 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
50 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
On-board Phase-Locked Loop (PLL)
The DAC165xQ has a single differential clock input to directly feed the digital and analog
clock tree of the device. When using the embedded PLL, a reference clock has to be
provided at this input. The mixed-signal PLL synthesizes the correct internal clocks with
very low jitter. The predivider (N) and post-divider (M) can be programmed to divider ratio
ranges from 1 to 16. The reference clock to the PLL should be 61.44 MHz for optimal PLL
performance. The DAC clock frequency can be calculated with Equation 15:
(15)
Figure 28 shows a conceptual view of the PLL. Digital control words that control the
oscillator frequency determine the output frequency of the PLL.
Clock frequency input range
The DAC165xQ can only operate in two modes:
Direct clocking mode:
The input clock frequency is limited to 1500 MHz
Divided clocking mode:
The input clock is internally divided by 2. The maximum input frequency is 3 GHz.
This mode allows the programming of the group delay feature.
Fig 27. LVDS clock configuration
Fig 28. PLL block diagram
100 Ω
LVDS
CLKIN_P
CLKIN_N
f DAC
FCW
MN
----------------
f
=
PFD
FILTERS
DCO
frequency
control word
fi
DIVIDER N
fref
DIVIDER M
fDAC
Table 23.
Examples
fi (MHz)
N
fref (MHz)
FCW
DCO (MHz)
M
FDAC (MHz)
122.88
2
61.44
72
4423.68
3
1474.56
122.88
2
61.44
80
4915.20
5
983.04


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