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DAC1653Q Datasheet(HTML) 52 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 52 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
52 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
Clock Domain Interface (CDI)
A CDI logic handles the error-free data transition from the WCLK clock domain to the
DCLK domain. It consists of 12 buffers that absorb the phase variation between the two
clocks. The reliability of the data transmission depends on the clock-frequency ratios and
therefore on the interpolation mode. The CDI must be set in the same mode as the
interpolation ratio to be properly configured. This mode is configured with register
CDI_CTRL .
Ideally, buffer number 11 is selected as the reference. If jitter of
1 clock cycle is injected
between the clocks occurs, the pointer can oscillate between buffers 10 and 0. If more
jitter is injected, the range increases to buffers 9 and 1, etc.
This buffer position can be monitored using register MON_DCLK .
The variation of the buffer location could also raise an interrupt (see interrupt section).
11.3 Analog quad DAC core
The DAC165xQ core consists of two DACs. Each of them can be independently set to
Power-down mode or Sleep mode if using the DAC in single channel mode is preferred
(DAC_X_AGAIN_PON).
Table 25.
Interpolation and CDI modes
Interpolation
CDI mode
Maximum input data rate
(Msps)
~1
Mode 0 (^2)
750
2
Mode 0 (^2)
750
4
Mode 1 (^4)
375
8
Mode 2 (^8)
187.5
Fig 29. Concept view of the CDI monitoring
0
1
2
3
4
5
6
7
8
9
10
11
nominal case
+1
-1


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