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DAC1653Q Datasheet(HTML) 56 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 56 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
56 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
11.6 Multiple Devices Synchronization (MDS); JESD204B subclass I
The MDS feature enables multiple DAC channels to be sampled synchronously and
phase coherently to within one DAC clock period. This feature is part of the JESD204B
standard but the implementation adds some unique features that simplify the PCB design.
11.6.1 Non-deterministic latency of a system
In a system using multiple DAC devices, there are numerous sources of timing
uncertainties. Figure 34 gives an overview of these uncertainties.
The sources of uncertainties are shared between the Transmitter device (TX), the
Receiver devices (RX), the PCB layout and the architectures of the JESD204B system
clocks. A single device can detect timing drift and uncertainties, but not at system level.
Therefore a synchronization process is required to enable the sytem to output the analog
signals of all the RX devices in a coherent way. Moreover, the system becomes
predictable if from one start-up to another one, the overall latency is deterministic.
The MDS feature of the DAC165xQ has been implemented in compliance with the
JESD204B subclass 1 specification to fulfill these requirements.
11.6.2 JESD204B system clocks
There are various system 'clocks' that are used in the JESD204B specification. However,
only one of them is seen at system level, the device clock, which is provided to the device.
The other clocks are related to the JESD204B standard and are used to
assemble/deassemble the data in octets and then in 10B words
(see JESD204B standard). Figure 35 and Table 26 show the relationship between them.
Fig 34. Timing uncertainties when using multiple DAC devices
S
E
R
I
L
A
TX
D
E
S
E
R
DLP
I
L
A
C
D
I
MDS
DSP
(DAC Dig)
Analog
DAC#1
S
E
R
I
L
A
TX
D
E
S
E
R
DLP
I
L
A
C
D
I
MDS
DSP
(DAC Dig)
Analog
DAC#2
SYNC
SYNC
CLK
Clock traces are not of the
same lengths
States Machines and Clock
tree need to be aligned
Deserializer Elastic buffers
add some unknown latency
Serializer Elastic buffers add
some unknown latency
Clocks Domain Interfaces add
some unknown uncertainties
Traces lengths are not
necessary of the same lengths


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