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DAC1653Q Datasheet(HTML) 57 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 57 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
57 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
From a system point of view, the TX and RX must share the same values for the internal
clocks but not necessarily the same device clocks. Figure 36 and Figure 37 show the
clocking scheme for an FPGA and a DAC working in an LMF-S = 421-1 configuration.
Fig 35. JESD204B system clocks
Table 26.
Relationship between various clocks
Clock name
Ratio with respect to
multi-frame clock
Comments regarding JESD204B specification
multi-frame clock
1
-
frame clock
 K
Ceil(17 / F)
 K  min(32, floor(1024 / F))
character clock
 F  K
F = 1 to 256
bit clock
 10  F  K
8b/10b encoding
sample clock
 S  K
S = 1 to 32
device clock
 D
D is integer
D
K
S
F
10
internal
MULTI-
FRAME
CLOCK
DEVICE
CLOCK
BIT CLOCK
CHARACTER
(OCTET)
CLOCK
FRAME
CLOCK
SAMPLE
CLOCK
Fig 36. Clocking scheme FPGA
10
7.5 Gbps
750 Msps
750 Msps
F = 1
DATA
CLOCK
750 Msps
25 MHz
D = 30
DAC
CLOCK
1.5 GHz
interpolation factor = x2
K = 30
S = 1
internal
device clock FPGA
LMFC FPGA


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