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DAC1653Q Datasheet(HTML) 60 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
Download  101 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 60 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
60 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
Figure 41 shows the LMFCs before and after alignment to the SYSREF clock.
Fig 40. Timing constraints for the SYSREF signal
sampling edge
device
clock
SYSREF
clock
tsu(min) th(min)
Fig 41. LMFCs before and after alignment to the SYSREF clock
before alignment
after alignment
device clock
DAC #1
device clock
DAC #1
device clock
FPGA
device clock
FPGA
device clock
DAC #2
device clock
DAC #2
LMFC
DAC #1
LMFC
DAC #1
LMFC
DAC #2
LMFC
DAC #2
LMFC
FPGA
LMFC
FPGA
SYSREF
clock


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