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DAC1653Q Datasheet(HTML) 61 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 61 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
61 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
11.6.4 MDS implementation
The DAC165xQ MDS implementation is based on two modules as described in Figure 42:
M1:
This module contains the SYSREF detector that is sampled at the DAC clock and the
control loop used to create a LMFCMDS signal. The control loop is clocked with the
digital clock. The digital clock equals DAC clock / 8.
Remark: The DAC clock and the device clock can differ when using the clock divider.
In this section DAC clock is referring to the final clock used to sample the DAC cores.
M2:
This module compares the phase of the LMFCRCV received from the JESD204B
digital lane processing to the phase of the LMFCMDS and shifts the position of the
buffer to align the data path to the LMFCMDS.
11.6.4.1 Capturing the SYSREF signal
Module M1 ensures the capture of the SYSREF signal at DAC clock accuracy. This is
done by an early-late detector and a control-loop. The control-loop must capture several
SYSREF edges to deliver an accurate LMFCMDS signal to the M2 module. The
Initialization of the control-loop is triggered by the edge detection of the SYSREF signal
(see Figure 43). It stands for 30 digital clock cycles, after which the capture process starts.
The capture is done during the capture window and is repeated at the end of every control
Fig 42. Modules of MDS implementation
0
JESD204B lanes
M2
ILA
DATARCV
LMFCRCV
-128
+128
BUFFER
DATAALIGNED
COMPARATOR
M1
SYSREF
DAC clock
digital clock
DET
CONTROL
LOOP
LMFCMDS
DAC


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