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DAC1653Q Datasheet(HTML) 62 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 62 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
62 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
loop period until the signal is locked. The SYSREF edge must occur within the capture
window. The capture process must be delayed to match this constraint. This is done by
programming the capture delay register.
Figure 44 shows an example on how to set up the M1 module.
The DAC165xQ requires the following parameters:
LMFC_PERIOD (register x0AA):
Period of the LMFC in digital clock cycles (e.g. 8
 8 ns)
Fig 43. Capturing the SYSREF signal
SYSREF
INITIALIZATION
control
loop
kick -off
control loop period
capture
window
capture
delay
control loop
LMFCMDS
LMFC period
Fig 44. Example of how to set up the M1 module
10
Internal
SYSREF
control loop
8
SYSREF
7.8125 MHz
R = 2
128 ns
LMFC
15.625 MHz
D = 64
DAC
CLOCK
1 GHz
64 ns
1 ns
K = 32
BIT CLOCK
5 Gbps
CHARACT.
CLOCK
500 Msps
F = 1
S = 1
DATA
CLOCK
500 Msps
FRAME
CLOCK
500 Msps
2 ns
2 ns
8 ns
DIGITAL
CLOCK
125 MHz
LMFCMDS
128 ns
control
loop
kick-off
INITIALIZATION
30 * 8 ns
capture
delay
capture
window
< 128 ns
128 ns
control loop period
64 ns
LMFC
period
JESD204B configuration for the DAC
Timing diagram related to the M1 module


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