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DAC1653Q Datasheet(HTML) 63 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
Download  101 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 63 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
63 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
CAPTURE_DELAY (register x0AC):
Must be tuned using the following equation:
Example:
The capture delay is expressed in digital clock period (for example 2
 8 ns)
Capture window and control loop period:
These are specified using MDS_WIN_HIGH and MDS_WIN_LOW registers
(respectively x0A9 and x0A8). They are expressed in digital clock cycles and must be
set using the following equations:
Remark: The capture window must be smaller than the SYSREF period.
At the end of the capture process, the LMFCMDS signal is provided to the M2 module and
the MDS_LOCK bit of the MDS status register is set to 1. If the M1 module cannot lock,
the MDS_BSY flag is kept high and a mute action can be held .
11.6.4.2 Aligning the LMFCs and the data
Module M2 ensures the phase alignment of the LMFCRCV to the closest LMFCMDS edge.
The LMFCRCV is issued from the digital lane processing by analyzing the ILA sequence
using the multi-frames /A/ symbols present. The transmitter (TX) is expected to have its
self-synchronization process to the global MFCSYSTEM. It generates the ILA sequence
based on the aligned LMFCTX. The total latency of the link is compounded of a fixed
value (due to PCB traces, devices internal fixed delays, etc.) and an undeterministic value
(due to elastic buffers, clocks domains interface, etc.). By buffering the data and the
LMFCRCV after the inter-lane alignment process, the M2 module is capable to adjust the
position of the buffer delay to match the recovered LMFCMDS.
Figure 45 shows the alignment process for two links. The two links have two different total
latencies but due to the LMFCTX and LMFCMDS phase synchronization to the MFCSYSTEM,
the various devices are capable to align to the same MFCSYSTEM edge in a fixed and
deterministic way.
initialization capture delay
+
n SYSREF period
=
30 8 ns

28 ns

+
2 128 ns
=
capture window
2
MDS_WIN _HIGH
1
+

=
control loop period
capture window MDS_WIN _LOW
1
++
=


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