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DAC1653Q Datasheet(HTML) 65 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
Download  101 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 65 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
65 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
In some cases, the latency between devices is small, but the edge is wrongly selected
due to the closest edge criteria. To avoid this, a LMFC preset delay can be applied on all
the LMFCMDS signals. It is important that all the DAC devices receive the same LMFC
preset value. If not the latency is not exactly the same. This parameter is set with the
LMFC_PRST register expressed in digital clock cycles. This value must be adjusted
manually for each newly designed system.
Fig 46. Wrong edge selection
R
A R
A
ILA
R
A R
A
ILA
RX #1
RX #2
K28.5
K28.5
alignment #1
alignment #1
LMFCRCV #1
LMFCRCV #2
ΔLBD = latency between
devices
MFCSYSTEM
= LMFCMDS #1
= LMFCMDS #2


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