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DAC1653Q Datasheet(HTML) 66 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
Download  101 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 66 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
66 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
11.6.4.3 Monitoring the MDS process
The buffer adjustment performed using the M1 and M2 modules can be read back using
the MDS_ADJ_DLY register . Bits 7 to 3 of this register represent the coarse delay
expressed in digital clock cycles whereas bits 2 to 0 represent the fine adjustment in DAC
clock cycles. The buffer adjustment has a default value of 80h.
11.6.4.4 Adding adjustment offset
The DAC165xQ allows adding an offset on top of the automatic adjustment. This is
available via register MDS_OFFSET_DLY . The offset range is from
16 to 15 digital clock
cycles. This offset value can be set at the start-up time as well as in at later period. This
enables compensating a layout error or adding a specific phase to one DAC device.
Another adjustment delay can be set but only after a first automatic alignment using the
manual adjustment delay register MDS_MAN_ADJ_DLY .
11.6.4.5 Selecting the SYSREF input port
The DAC165xQ incorporates two SYSREF differential ports: SYSREF_E_P/N (East side
of the device) and SYSREF_W_P/N (West side of the device). One of these ports can be
selected as the input for the SYSREF signal. Which port is selected is device dependent.
One DAC165xQ uses the Eastern SYSREF while another DAC165xQ uses the Western
SYSREF (see Figure 48).
a. Wrong edge selection
b. Correct edge selection with the LMFC preset
delay
Fig 47. Edge selection
R
A R
A
ILA
R
A R
A
ILA
RX #1
RX #2
K28.5
K28.5
alignment #1
alignment #2
LMFCRCV #1
LMFCRCV #2
ΔLBD = latency between
devices
MFCSYSTEM
= LMFCMDS #1
= LMFCMDS #2
R
A R
A
ILA
R
A R
A
ILA
LMFC preset delay
RX #1
RX #2
K28.5
K28.5
alignment #1
alignment #2
LMFCRCV #1
LMFCRCV #2
ΔLBD = latency between
devices
= LMFCMDS #1
= LMFCMDS #2
MFCSYSTEM


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