Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.NET

X  

Preview PDF Download HTML

DAC1653Q Datasheet(HTML) 67 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
Download  101 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
Logo 

DAC1653Q Datasheet(HTML) 67 Page - Integrated Device Technology

Zoom Inzoom in Zoom Outzoom out
Go To Page :
/ 101 page
background image
DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
67 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
Register MDS_EAST_WEST is used to select between the East port or the West port.
Each SYSREF input buffer has an optional internal differential resistor termination of
about 100
. This resistor can be enabled with registers MDS_SEL_EAST_RT and
MDS_SEL_WEST_RT . The clock edge (rising/falling) on which the SYSREF signal is
sampled can also be selected using registers MDS_SEL_FE_EAST and
MDS_SEL_FE_WEST .
11.7 Interrupts
In some cases it may be useful if the host-controller is notified that a certain internal event
has taken place by means of an interrupt . The DAC165xQ includes a simple interrupt
(INTR) controller for this purpose.
The INTR-signal can be made available on one of the I/O pins. The polarity is
programmable .
11.7.1 Events monitored
The DAC165xQ monitors various internal events and indicates their occurrence in the
INTR_FLAGS_XY registers . The following event can be observed:
INTR_DLP_XY:
Digital Lane Processing (DLP) has its own interrupt controller. The result of this slave
controller is provided to the main interrupt controller through the INTR_DLP_XY bit .
MDS_BSY_XY and MDS_BSY_XY:
Refer to the activity of the MDS controller. During the synchronization phase, the
MDS_BUSY signal is high, and come low once finished.
– MDS_BSY_XY reflects the start of the activity of the MDS controller
– MDS_BSY_XY reflects the end of the activity of the MDS controller
TEMP_ALARM_XY:
Fig 48. SYSREF differential ports
1
18
54
49
48
37
19
36
72
55
SYSREF GENERATOR DEVICE
SYSREF_E
1
18
54
6
7
37
19
36
72
55
SYSREF_W
DAC
DEVICE #0
DAC
DEVICE #1


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download




Link URL



Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Bookmark   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn