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DAC1653Q Datasheet(HTML) 71 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 71 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
71 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
When register INTR_DLP_XY is invoked, the “FLAGS” registers must be read to
determine which event has occurred:
An INTR_EN_NIT_XY event is related to the DEC_NIT_ERR_P_LNx_XY bits of
register DEC_FLAGS_XY
An INTR_EN_DISP_XY event is related to the DEC_DISP_ERR_P_LNx_XY bits of
register DEC_FLAGS_XY
An INTR_EN_KOUT_XY event is related to the DEC_KOUT_L_LNx_XY bits of
register KOUT_FLAG_XY
An INTR_EN_KOUT_UNEXP_XY event is related to the
DEC_KOUT_UNEXP_L_LNx_XY bits of register KOUT_UNEXP_FLAG_XY
An INTR_EN_K28_7 event is related to the K28_7_LNx bits of register K28_FLAG
An INTR_EN_K28_5 event is related to the K28_5_LNx bits of register K28_FLAG
An INTR_EN_K28_3 event is related to the K28_3_LNx bits of register K28_FLAG
An INTR_EN_MISC_XY event is related to the CS_STATE_LNx_XY bits of register
CS_STATE_LN_XY and the ILA_BUFF_ERR_LNx_XY bits of register
ILA_BUFF_ERR_XY register
All flag bits can be reset using register RST_FLAGS_MON_XY .
11.7.4 JESD204B physical and logical lanes
The DAC165xQ integrates a JESD204B serial interface with a high flexibility of
configuration.
Because of various implementations for JESD204B transmitter devices, a flexible
configuration of the physical lanes is required. This configuration allows the lane polarity
to invert individually and to arbitrary swap the lane order. Identifying the lane numbers can
be confusing because of the lane swapping. Two terms, Physical and Logical, are used in
this document to explicitly identify the lanes.
Physical lanes:
The DAC165xQ integrates four JESD204B serial receivers that are referenced via the
pinning information (see Figure 2).
The descrambler can be enabled or disabled.
Fig 50. JESD204B receiver
10b
10b
SYNC_OUT
internal
configuration
interface
logical lanes
physical lanes
lane
configuration
extraction
DES
BUFFERING
lane0
lane1
lane2
lane3
10b
16b
16b
SYNC
AND
WORD
ALIGN
8b
10b/8b
DECODER
8b
8b
8b
8b
8b
8b
DESCRAMBLER
DESCR_EN_XY
RX CONTROLLER


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