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DAC1653Q Datasheet(HTML) 76 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 76 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
76 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
11.7.5.5 Word locking and Code Group Synchronization (CGS)
When the bits are received from the RX physical layer, DLP has to identify the MSB and
LSB boundaries of the 10-bit codes from the bitstream. This can be monitored using the
LOCK_CNT_MON_LN01_XY and LOCK_CNT_MON_LN23_XY registers .
When all lanes are locked, the values of the registers are stable and the code group
synchronization process can start. This process is described by the JESD204B
specification and is represented by the state machine shown in Figure 52.
DAC C/D
logical lane 0
physical lane 0
physical lane 0
physical lane 0
or
or
or
physical lane 1
physical lane 1
physical lane 1
or
or
or
physical lane 2
physical lane 2
physical lane 2
or
or
or
physical lane 3
physical lane 3
physical lane 3
logical lane 1
physical lane 0
not used
not used
or
physical lane 1
or
physical lane 2
or
physical lane 3
logical lane 2
physical lane 0
physical lane 0
not used
or
or
physical lane 1
physical lane 1
or
or
physical lane 2
physical lane 2
or
or
physical lane 3
physical lane 3
logical lane 3
physical lane 0
not used
not used
or
physical lane 1
or
physical lane 2
or
physical lane 3
Table 29.
Lane mapping between logical and physical lanes regarding the L value
L
4
2
1


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