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DAC1653Q Datasheet(HTML) 79 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 79 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
79 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
The inter-lane alignment synchronization is enabled by default, but it can be disabled
using bit ILA_SYNC_XY of register ILA_CTRL_1_XY register . When ILA is disabled, the
lane-alignment can be done manually using registers MAN_ALIGN_P_LN_1_0_XY . The
manual mode must first be enabled using bit FORCE_ALIGN_XY of register
FORCE_ALIGN_XY .
The ILA module uses a 16-bit buffer for each lane. The first /A/ symbol received over the
lanes is used as reference. The /A/ symbols of the other lanes, which are received later,
are compared to the first one to be all aligned. The initial location of the symbols is
predefined by the INIT_ILA_BUFF_PNTR_L_LN01_XY and
INIT_ILA_BUFF_PNTR_L_LN23_XY registers . The alignment can be monitored with the
ILA_MON_L_LNn_XY bits of the ILA_MON_L_LN10 and ILA_MON_L_LN32 registers . If
the lane difference is too great, a buffer out of range error occurs, which can be monitored
with bits ILA_BUFF_ERR_L_LNx_XY of the ILA_BUFF_ERR_XY register . In this specific
case, a reinitialization of the full link can be requested by setting the
REINIT_ILA_L_LNx_XY bits of the REINIT_CTRL_XY register.
The JESD204B specification also mentions a dynamic realignment mode where a
monitoring process is checking the /A/-symbol location. This can realign the data stream if
two successive /A/ symbols are found at the same new position. By default this monitoring
and correction process is disabled to avoid any moving latency over the link, but one can
enable the feature by setting bit DYN_ALIGN_EN_XY of the FORCE_ALIGN_XY register
.
11.7.5.8 Character replacement
Character replacement, as specified by the JESD204B specification, can occur at the end
of the frame (K28.7 or /F/ symbol) or at the end of the multi-frame (K28.3 or /A/ symbol).
By default this feature is enabled, but it can be disabled using bit FRAME_ALIGN_EN_XY
of the FORCE _LOCK register .
Remark: The DAC165xQ can handle multi-frame length values (K) between
and 32 but with the restriction that the number of octets in a multi-frame must always be
even. This implies that if F = 1, a value of K = 17 is not allowed. When F = 1 only even
values > 17 are allowed. Working with F = 1 and K = 17 often implies that the character
replacement process is not reliable.
11.7.5.9 Sample assembly
Sample assembly handles the assembly of the data based on the LMF parameters
described by the LMF_CTRL register . The following configurations are supported:
LMF = 421
LMF = 422
LMF = 222
Table 32.
Overview of generic parts of register addresses
DAC A/B
DAC C/D
lane 0
nnn = 012
nnn = 032
lane 1
nnn = 013
nnn = 033
lane 2
nnn = 014
nnn = 034
lane 3
nnn = 015
nnn = 035
ceil 17 F



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