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DAC1653Q Datasheet(HTML) 81 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 81 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
81 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
During the data transmission phase, only K28.3 (/A/) and K28.7 (/F/) symbols are
expected. Sometimes (e.g. wrong bit transmission), a code group is interpreted as a K
character that is not K28.3 or K28.7. If this occurs a KOUT_UNEXP flag is asserted that
can be read using bits DEC_KOUT_UNEXP_L_LNx_XY of the KOUT_UNEXP_FLAG_XY
(.
All the previous flags can be reset using the RST_FLAGS_MON_XY register . Detection
of them can also assert the DLP interrupt .
11.7.6 Monitoring and test modes
The DAC165xQ embeds various monitoring and test modes that are useful during the
prototyping phase of a system.
Remark: The test capability linked to observing specific characters, errors or state
machine statuses is not reviewed in this section. It is up to the reader to define specific
modes based on the DAC165xQ capability.
11.7.6.1 Flag counters
Due to the high data rate of the JESD204B serial interface, it is hard to monitor events that
occur on the lanes in real time. Four multi-purpose counters have been added to the
design to help this monitoring. Each counter is 16 bits wide and is linked to one lane. It
increments its value each time a specific event occurs. These flags counters can be read
using the FLAG_CNT_LNx_XY registers and reset using the
RST_CTRL_FLAG_CNT_LNx_XY bits of the CTRL_FLAG_CNT_LNxx registers The
flag counters can also be reset automatically when DLP is reset by setting the
AUTO_RST_FLAG_CNTS_XY bit of register RST_BUFF_ERR_FLAGS to logic 1.
The specification of the event that increments the counter is done by setting the
SEL_CTRL_FLAGS_CNT_LNxx_XY bits of the CTRL_FLAG_CNT_LNxx_XY registers
to one of the sources described in Table 33.
When the counter is reaching its maximum value (0xFFFF), this value is held until the next
counter reset. Bit HOLD_FLAG_CNT_EN_XY of the RST_BUFF_ERR_FLAGS_XY
register gives two options for when a counter reaches the maximum value.
Table 33.
Counter source
Default settings are shown highlighted.
SEL_CFC_LNn[2:0]
Source
000
not-in-table error
001
disparity error
010
K symbol not found
011
unexpected K symbol found
100
K28_7 (/F/) symbol found
101
K28_5 (/K/) symbol found
110
K28_3 (/A/) symbol found
111
K28_0 (/R/) symbol found


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