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DAC1653Q Datasheet(HTML) 84 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 84 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
84 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
11.7.6.4 DLP strobe
The data coming out of the ILA module can be sampled by setting the DLP_STROBE_XY
bit of the MISC_CTRL register . On each lane two octets are stored, which can be read
out through registers P_LNxx_SMPL_MSB and P_LNxx_SMPL_LSB . The selection of
the lane to read out the data is done by registers P_LN10_SEL and P_LN32_SEL .
11.7.7 IO-mux
The DAC165xQ uses two general purpose pins, IO0 and IO3. IO0 is always an output.
IO1 can be configured as an input or as an output by setting the IO_EN bit of the
EHS_CTRL register .
When acting as an output, the two IO pins are multiplexed to internal signals that can be
useful for debug purposes. Table 36 shows the main configuration when using bits
IO_SEL_x of the IO_MUX_CTRL_x register. The definitions of the three registers depend
of the "Indicator" and the "Range" values used to specify the Signal that is sent through
pins IO0 and IO1 (see tables below).
11.7.8 DLP latency
The variable delay (latency uncertainty) is the result of uncertainties and variation in
design implementations along the path between the transmit logic device and the
DAC165xQ. The Inter-Lane Alignment (ILA) module present in Digital Layer Processing
(DLP) realigns the input streams to the last data received.
Table 36.
Definition of IO_SEL registers
Register name
b7
b6
b5
b4
b3
b2
b1
b0
IO_SEL_4
IO3 indicator[1:0] IO2 indicator[1:0] IO1 indicator[1:0] IO0 indicator[1:0]
IO_SEL_3
IO3 range[7:0]
IO_SEL_2
IO2 range[7:0]
IO_SEL_1
IO1 range[7:0]
IO_SEL_0
IO0 range[7:0]
Table 37.
Output signals for combination of indicators and ranges
Indicator[1:0]
Range[7:0]
Output signal
00
xxxx xxx0
IO0: WCLK
IO1: DCLK
00
xxxx 0011
synchronization
10
1111 0000
end of ILA
10
1111 0001
end of ILA
11
1100 0000
interrupt
11
1100 0001
interrupt
11
1111 even
IO0: fixed to logic 1
IO1: fixed to logic 0
11
1111 odd
IO0: fixed to logic 0
IO1: fixed to logic 1


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