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DAC1653Q Datasheet(HTML) 92 Page - Integrated Device Technology

Part No. DAC1653Q
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1653Q Datasheet(HTML) 92 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
92 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
11.10 Design recommendations
11.10.1 Power and grounding
Use a separate power supply regulator for the generation of the 1.2 V analog power
(pins 43, 48. 51. 56) and the 1.2 V digital power (pins 7, 10, 33, 36) to ensure optimal
performance.
High-speed input lanes are powered by a 1.2 V power supply that can require a dedicated
power supply. Pins 15, 16, 19, 22, 25, 28 can be connected to either the global 1.2 V
power supply or to a dedicated one.
Also, include individual LC decoupling for the following six sets of power pins:
VDDA(1V2)
LDO low noise:
– DAC AB (pins 65, 68, 69, 72)
– DAC CD (pins 55, 58, 59, 62)
– BIASING (pins 50, 53)
– CLOCK (pin 2)
VDDA(3V3)
LDO low noise:
– Output AB (pins 1, 64)
– Output CD (pins 54, 63)
VDDA(3V3)
LDO low noise:
– PLL (pin 5)
VDDD(1V2)
Switch supply:
– DIGITAL (pins 8, 15, 40, 47)
– SYNC output (pin 39)
– JESD204B input (pin 16, 23, 32)
– IO/SPI (pin 41)
Use at least two capacitors for each power pin decoupling. Locate these capacitors as
close as possible to the DAC1658Q power pins.
Use a separate LDO for the generation of the 1.2 V analog power (VDDA(1V2)) and the
1.2 V digital power (VDDD(1V2)) to ensure the best performance.
The die pad is used for both the power dissipation and electrical grounding. Insert several
vias (typically 7
 7 to connect the internal ground plane to the top layer die area.


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