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DAC1658Q1G5NAGA Datasheet(HTML) 23 Page - Integrated Device Technology

Part No. DAC1658Q1G5NAGA
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1658Q1G5NAGA Datasheet(HTML) 23 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
23 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
11. Application information
11.1 General description
The DAC165xQ is a quad 16-bit DAC operating up to 1.50 Gsps. A maximum input data
rate up to 750 Msps is supported to enable more capability for wideband and multicarrier
systems. The incorporated quadrature modulators and 40-bit Numerically Controlled
Oscillators (NCOs) simplify the frequency selection of the system. This is also possible
because of the
2, 4 or 8 interpolation filters which remove undesired images.
The DAC165xQ embeds four DAC channels (A, B, C and D) that can be configured as a
single quad DAC (A/B/C/D) or two dual DACs (A/B and C/D). The two NCOs are linked to
the A/B and the C/D dual DACs, respectively. Regarding the quad/dual mode used, the
eight JESD204B lanes are configured as one single link configuration JESD204 link (one
SYNC signal for a specified number of lanes), or dual link configuration JESD204B links
(two SYNC signals associated with a specified number of lanes).
The DAC165xQ supports the following JESD204B key features:
10-bit/8-bit decoding
Code group synchronization
Initial-Lane Alignment (ILA)
1 + x14 + x15 scrambling polynomial
Character replacement
TX/RX synchronization management via synchronization signals
Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) device
Number L of serial lanes: 1, 2, 4, 8 (see LMF configuration table)
Number M of data converters: 1, 2 or 4 (see LMF configuration table)
Number F of octets per frame: 1, 2, 4, 6, 8 (see LMF configuration table)
Number S of samples per frame: 1, 2 (see LMF configuration table)
Embedded test pattern (PRBS7; PRBS15; PRBS23, PRBS31, JTSPAT, STLTP)
The DAC165xQ can be interfaced with any logic device that features high-speed
SERializer/DESerializer (SERDES) functionality. This macro is now widely available in
Field-Programmable Gate Array (FPGA) of different vendors. Standalone SERDES ICs
can also be used.
The device includes polarity swapping for each of the lanes and additionally offers lane
swapping to enhance the intrinsic board layout simplification of the JESD204B standard.
Each physical lane can be configured logically as any lane number.
This device is MCDA-ML compliant, offering inter-lane alignment between several
devices. An IDT proprietary mechanism in combination with the JESD204B subclass I
clause enables maintenance of sample alignment between devices up to the final analog
output stage. Output samples are automatically aligned to the SYSREF signal generated
by a dedicated IC or by the FPGA itself. A system with several DAC165xQs can produce
data with a guaranteed alignment of 1 DAC output clock period. The DAC165xQ
incorporates two differential SYSREF ports (located on opposite sides of the IC). These


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