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DAC1658Q1G5NAGA Datasheet(HTML) 31 Page - Integrated Device Technology

Part No. DAC1658Q1G5NAGA
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1658Q1G5NAGA Datasheet(HTML) 31 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
31 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
[1]
The RESET_N signal is not linked to the SPI interface, but enables the reset of the registers to the default
values.
11.2.2 Main device configuration
The registers of block MAIN are used for the main configuration of the DAC165xQ.
At start-up, the two clocks WCLK and DCLK are forced to reset states to avoid that the
DAC outputs any dummy signal through bits FORCE_RST_DCLK and
FORCE_RST_WCLK of the MAIN_CTRL register . The device configuration has to be
done before releasing these two clocks.
Here are some guidelines to ensure correct SPI programming. As DCLK and WCLK are
kept to reset the programming sequence of the registers is not important:
<tbd>
Other SPI configurations can be added using these basic settings.
Table 13.
SPI timing characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fSCLK
SCLK frequency
-
-
25
MHz
tw(SCLK)
SCLK pulse width
30
-
-
ns
tsu(SCS_N)
SCS_N set-up time
20
-
-
ns
th(SCS_N)
SCS_N hold time
20
-
-
ns
tsu(SDIO)
SDIO set-up time
10
-
-
ns
th(SDIO)
SDIO hold time
5
-
-
ns
tw(RESET_N)
RESET_N pulse width
[1] 30
-
-
ns
Fig 13. Main controls
IO_SEL_2
IO0
IO_SEL_0
IO0
IO_SEL_1
IO_EN 0
IO_EN 1
INTERFACE
DAC DSP
MON_DCLK
BLOCK 0060h
MON_DCLK_STOP
CDI
CDI_MOD
^2 mode
^4 mode
^8 mode
DLP
SR_CDI
RX IP
AUTO_CAL_EQZ
AUTO_CAL_RT
Q_DC_LVL_XY
Q_LVL_CTRL_XY
DAC B/D
I_DC_LVL_XY
I_LVL_CTRL_XY
DAC A/C
VIN_AB_P3/VIN_CD_P3
VIN_AB_N3/VIN_CD_N3
DCLK
(see block 0020h)
WCLK
(see block 0020h)
FORCE_RST_WCLK
RST_EXT_WCLK_TIME
FORCE_RST_DCLK
RST_EXT_DCLK_TIME
START-UP MANAGEMENT
VIN_AB_P2/VIN_CD_P2
VIN_AB_N2/VIN_CD_N2
VIN_AB_P1/VIN_CD_P1
VIN_AB_N1/VIN_CD_N1
VIN_AB_P0/VIN_CD_P0
POFF_RX
MAN_PON_CTRL
L0
L1
L2
L3
VIN_AB_N0/VIN_CD_N0
Eq
Eq
Eq
Eq
BLOCK 0040h: MAIN CONTROLS


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