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DAC1658Q1G5NAGA Datasheet(HTML) 41 Page - Integrated Device Technology

Part No. DAC1658Q1G5NAGA
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1658Q1G5NAGA Datasheet(HTML) 41 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
41 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
The mute feature is set by enabling bit MUTE_EN_XY in register MUTE_CTRL_0_XY .
Mute events
The MUTE action is triggered by one of the following mute events. Each of them is linked
to either an error detection, a status change or signal power monitoring:
SPI_SW_MUTE_XY:
Software event that can be requested by the host interface through the SPI bus.
RF_EN_XY:
Hardware event that can be requested by the host interface through pins SR_TG_AB
and SR_TG_CD.
CLK_MON_XY:
Event linked to the monitoring of the clocks in the receiver physical layer control block.
MON_DCLK_ERR_XY:
Event triggered when a clock error occurs in the CDI .
CA_ERR_XY:
Event triggered when a clock error occurs in the DLP .
TEMP_ALARM_XY:
Event triggered when the temperature sensor measures a temperature that exceeds
the threshold value. TEMP_SEL_MAN_XY must be specified first.
ERR_RPT_FLAG_XY:
Event triggered when DATA_INVALID is detected by the DLP .
LVL_DET_OR_XY:
Fig 21. Auto-mute state machine
normal operating mode
digital gains are
equal to initial values
one of the « mute events »
is triggered
digital gains set
to initial values
IDLE
DEMUTE
WAIT
MUTE
« wait period » elapsed and
« mute event » deasserted
digital gains to
initial values within
specified « mute rate »
digital gains kept
at zero during
« wait period » time
digital gains
equal zero
digital gains decreased
to zero within specified
« mute rate »
one of the « mute events »
is triggered


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