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DAC1658Q1G5NAGA Datasheet(HTML) 58 Page - Integrated Device Technology

Part No. DAC1658Q1G5NAGA
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1658Q1G5NAGA Datasheet(HTML) 58 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
58 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
As all clocks can be derived from the Multi-Frame Clock (MFC), this clock becomes the
reference for a JESD204B system. Each device used in the system has its own local
version of the MFC. These local version are called Local Multi-Frame Clock (LMFC). Due
to the timing uncertainties the phase relationships between all the device LMFCs are
unknown. The goal of MDS is to be able to realign all LMFCs in a fixed and accurate way.
11.6.3 SYSREF clock
To align all the LMFCs within the system, a new clock named SYSREF (SYStem
REFerence) is used. This clock is linked to the multi-frame clock by a ratio R. It is a low
frequency signal. However, the edges of the signal must be sharp enough as it is sampled
by the device clock.
Fig 37. Clocking scheme DAC
10
7.5 Gbps
750 Msps
750 Msps
F = 1
DATA
CLOCK
750 Msps
25 MHz
D = 60
DAC
CLOCK
1.5 GHz
interpolation factor = x2
K = 30
S = 1
internal
LMFC DAC #1
device clock
DAC #2
Fig 38. SYSREF clock
D
K
S
F
10
R
SYSREF
CLOCK
MULTI-
FRAME
CLOCK
DEVICE
CLOCK
BIT CLOCK
CHARACTER
(OCTET)
CLOCK
FRAME
CLOCK
SAMPLE
CLOCK
internal


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