DAC1658Q1G5NAGA datasheet(59/101 Pages) IDT

Part #	DAC1658Q1G5NAGA

Description	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50

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Manufacturer	IDT [Integrated Device Technology]

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59 / 101 page

DAC1653Q/DAC1658Q

Advance data sheet

Rev. 1.03 — 13 May 2013

59 of 101

Integrated Device Technology

DAC1653Q/DAC1658Q

Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps

The SYSREF signals must be propagated to all the devices of the system. They are used

to release the LMFC, so they are all aligned over the devices. The SYSREF signal is

sampled by the device clocks. To ensure that all phases of the signals are aligned at the

source, the SYSREF signals and the device clocks must be generated from the same

clock IC.

All the JESD204B devices sample the SYSREF signal with their own device clocks. The

edge detection of the SYSREF signal is used as a system timing reference and the device

phase-align their LMFCs to the closest edge of the SYSREF. To ensure an accurate

alignment within all devices, the SYSREF signal must show the same phase at the input

port of all the devices to synchronize. Therefore, the trace lengths of the SYSREF signals

must be equal for all the DAC devices. As the SYSREF signal is sampled by the device

clock, the minimum setup (tsu(min)) and hold (th(min)) time are specified with respect to the

Device Clock timing (see Figure 40).

Fig 39. System

10

FPGA

7.5 Gbps

750 Msps

DATA

CLOCK

750 MHz

DATA

CLOCK

750 MHz

DATA

CLOCK

750 MHz

F = 1

S = 1

internal

K = 30

25 MHz

R = 5

D = 30

D = 60

FPGA

CLOCK

750 MHz

SYSREF

CLOCK

5 MHz

25 MHz

K = 30

DAC #1

DAC #2

DAC

CLOCK

1.5 Gsps

DAC

CLOCK

1.5 Gsps

All clocks and SYSREF signals are

generated from the same device

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DAC1658Q1G5NAGA Datasheet(PDF) 59 Page - Integrated Device Technology

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