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DAC1658Q1G5NAGA Datasheet(HTML) 68 Page - Integrated Device Technology

Part No. DAC1658Q1G5NAGA
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1658Q1G5NAGA Datasheet(HTML) 68 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
68 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
Indicates that the temperature measured by the on-chip temperature sensor exceeds
the threshold temperature .
LVL_DET_OR_XY:
Indicates that one of the level detectors is enabled.
CA_ERR_XY:
Indicates a DLP clock error.
CLK_MON_XY:
Indicates a CDI clock error.
DCLK_ERR_MON_XY:
Indicates a drift on the DCLK as specified by register
INTR_DCLK_MON_RANGE_XY .
ERR_RPT_FLAG_XY:
Indicates the transmission of error reporting via the SYNCB interface.
ALARM_STATE_XY:
Indicates when an auto-mute event occurs .
11.7.2 Enabling interrupts
An indication if an 0
1 transition of the corresponding monitor- or error indicator activates
the INTR-signal can be given using the INTR_EN_XY registers . The INTR_FLAGS_XY
registers indicate which of the selected events has invoked the interrupt. When bit
INTR_RST_XY is set to 1 the flags and the INTR-signal are reinitialized.
11.7.3 Digital Lane Processing (DLP) interrupt controller
The DLP has its own interrupt controller that reports to the main interrupt controller. This
DLP interrupt controller is managed from the SPI registers of block x00E0 (see Figure 49).


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