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DAC1658Q1G5NAGA Datasheet(HTML) 69 Page - Integrated Device Technology

Part No. DAC1658Q1G5NAGA
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1658Q1G5NAGA Datasheet(HTML) 69 Page - Integrated Device Technology

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Block 00E0h = DAC A/B
Block 02E0h = DAC C/D
Block 04E0h = All DACs
Fig 49. Digital lane processing monitoring overview
BLOCK 00E0h/02E0h/04E0h: RX DLP MONITORING
ILA MONITORING
ILA MON LANE 0
ILA_MON_L_LN0_XY
ILA_BUFF_ERR_L_LN0_XY
DECODER LANE 0
DEC_NIT_ERR_P_LN0_XY
DEC_DISP_ERR_P_LN0_XY
DEC_KOUT_L_LN0_XY
DEC_KOUT_L_UNEXP_LN0_XY
K28_7_P_LN0_XY
K28_5_P_LN0_XY
K28_4_P_LN0_XY
K28_3_P_LN0_XY
K28_0_P_LN0_XY
DECODER LANE 1
DEC_NIT_ERR_P_LN1_XY
DEC_DISP_ERR_P_LN1_XY
DEC_KOUT_L_LN1_XY
DEC_KOUT_UNEXP_L_LN1_XY
K28_7_P_LN1_XY
K28_5_P_LN1_XY
K28_4_P_LN1_XY
K28_3_P_LN1_XY
K28_0_P_LN1_XY
DECODER LANE 2
DEC_NIT_ERR_P_LN2_XY
DEC_DISP_ERR_P_LN2_XY
DEC_KOUT_L_LN2_XY
DEC_KOUT_UNEXP_L_LN2_XY
K28_7_P_LN2_XY
K28_5_P_LN2_XY
K28_4_P_LN2_XY
K28_3_P_LN2_XY
K28_0_P_LN2_XY
DECODER LANE 3
DEC_NIT_ERR_P_LN3_XY
DEC_DISP_ERR_P_LN3_XY
DEC_KOUT_L_LN3_XY
DEC_KOUT_UNEXP_L_LN3_XY
K28_7_P_LN3_XY
K28_5_P_LN3_XY
K28_4_P_LN3_XY
K28_3_P_LN3_XY
K28_0_P_LN3_XY
RESET
RST_K28_FLAGS_P_LN0_XY
RST_K28_FLAGS_P_LN1_XY
RST_K28_FLAGS_P_LN2_XY
RST_K28_FLAGS_P_LN3_XY
RST_KOUT_UNEXP_FLAGS_XY
RST_KOUT_FLAGS_XY
RST_DSIP_ERR_FLAGS_XY
RST_NIT_ERR_FLAGS_XY
ILA MON LANE 1
ILA_MON_L_LN1_XY
ILA_BUFF_ERR_L_LN1_XY
ILA MON LANE 2
ILA_MON_L_LN2_XY
ILA_BUFF_ERR_L_LN2_XY
ILA MON LANE 3
ILA_MON_LN3_XY
ILA_BUFF_ERR_L_LN3_XY
10B/8B DECODER MONITORING
FLAG COUNTER LANE 0
FLAG_CNT_LN0_XY
RST_CTRL_FLAG_CNT_LN0_XY
SEL_CTRL_FLAG_CNT_LN0_XY
ser_p_ln0, cm_0, nit_err_p_ln0, disp_err_p_ln0,
kout_ln0, kout_unexp_I_ln0, k28_7_p_ln0,
k28_5_p_ln0, k28_3_p_ln0, k28_0_p_ln0,
FLAG COUNTER LANE 1
FLAG_CNT_LN1_XY
RST_CTRL_FLAG_CNT_LN1_XY
SEL_CTRL_FLAG_CNT_LN1_XY
ser_p_ln1, cm_1, nit_err_p_ln1, disp_err_p_ln1,
kout_I_ln1, kout_unexp_I_ln1, k28_7_p_ln1,
k28_5_p_ln1, k28_3_ln1, k28_0_p_ln1,
FLAG COUNTER LANE 2
FLAG_CNT_LN2_XY
RST_CTRL_FLAG_CNT_LN2_XY
SEL_CTRL_FLAG_CNT_LN2_XY
ser_p_ln2, cm_2, nit_err_p_ln2, disp_err_p_ln2,
kout_I_ln2, kout_unexp_I_ln2, k28_7_p_ln2,
k28_5_p_ln2, k28_3_p_ln2, k28_0_p_ln2,
FLAG COUNTER LANE 3
FLAG_CNT_LN3_XY
RST_CTRL_FLAG_CNT_LN3_XY
SEL_CTRL_FLAG_CNT_LN3_XY
ser_p_ln3, cm_3, nit_err_p_ln3, disp_err_p_ln3,
kout_I_ln3, kout_unexp_I_ln3, k28_7_p_ln3,
k28_5_p_ln3, k28_3_p_ln3, k28_0_p_ln3,
FLAG COUNTERS
SER
SER_LVL_XY
(I/Q DC levels used for SER test are specified on page x0A)
DLP INTERRUPT
INTR_RST_XY
INTR_MOD_XY:
intr depends on ln0
intr depends on ln1
intr depends on ln2
intr depends on ln3
intr depends on ln0 or ln2
intr depends on ln0 or ln1 or ln2 or ln3
no interrupt
SER_MOD_XY
INTR_EN_NIT_XY
INTR_EN_DISP_XY
INTR_EN_KOUT_XY
INTR_EN_KOUT_UNEXP_XY
INTR_EN_K28_7_XY
INTR_EN_K28_5_XY
INTR_EN_K28_3_XY
INTR_EN_MISC_XY


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