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DAC1658Q1G5NAGA Datasheet(HTML) 72 Page - Integrated Device Technology

Part No. DAC1658Q1G5NAGA
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1658Q1G5NAGA Datasheet(HTML) 72 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
72 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
DAC A/B physical lane 0 refers to the signal coming from pins VIN_AB_P0 and
VIN_AB_N0
DAC_A/B physical lane 1 refers to the signal coming from pins VIN_AB_P1 and
VIN_AB_N1
DAC A/B physical lane 2 refers to the signal coming from pins VIN_AB_P2 and
VIN_AB_N2
DAC A/B physical lane 3 refers to the signal coming from pins VIN_AB_P3 and
VIN_AB_N3
DAC C/D physical lane 0 refers to the signal coming from pins VIN_CD_P0 and
VIN_CD_N0
DAC C/D physical lane 1 refers to the signal coming from pins VIN_CD_P1 and
VIN_CD_N1
DAC C/D physical lane 2 refers to the signal coming from pins VIN_CD_P2 and
VIN_CD_N2
DAC C/D physical lane 3 refers to the signal coming from pins VIN_CD_P3 and
VIN_CD_N3
Logical lanes:
The DAC165xQ incorporates a Swap lanes module (see Figure 7) that allows a
remapping of the lane numbers to be compatible with the system implementation.
DAC A/B logical lane 0 refers to the lane specified with the LN_SEL_P_LN0_XY bits
in register LN_SEL_XY (00CDh)
DAC A/B logical lane 1 refers to the lane specified with the LN_SEL_P_LN1_XY bits
in register LN_SEL_XY (00CDh)
DAC A/B logical lane 2 refers to the lane specified with the LN_SEL_P_LN2_XY bits
in register LN_SEL_XY (00CDh)
DAC A/B logical lane 3 refers to the lane specified with the LN_SEL_P_LN3_XY bits
in register LN_SEL_XY (00CDh)
DAC C/D logical lane 0 refers to the lane specified with the LN_SEL_P_LN0_XY bits
in register LN_SEL_XY (02CDh)
DAC C/D logical lane 1 refers to the lane specified with the LN_SEL_P_LN1_XY bits
in register LN_SEL_XY (02CDh)
DAC C/D logical lane 2 refers to the lane specified with the LN_SEL_P_LN2_XY bits
in register LN_SEL_XY (02CDh)
DAC C/D logical lane 3 refers to the lane specified with the LN_SEL_P_LN3_XY bits
in register LN_SEL_XY (02CDh)
The following naming convention are used to distinguish between the physical lanes and
the logical lanes in the SPI registers: “P_LNx” is used to identify the physical lanes.
“L_LNx” is used to identify the logical lanes. “x” stands for the lane number in both cases.


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