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DAC1658Q1G5NAGA Datasheet(PDF) 77 Page - Integrated Device Technology |
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DAC1658Q1G5NAGA Datasheet(HTML) 77 Page - Integrated Device Technology |
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77 / 101 page  DAC1653Q/DAC1658Q © IDT 2013. All rights reserved. Advance data sheet Rev. 1.03 — 13 May 2013 77 of 101 Integrated Device Technology DAC1653Q/DAC1658Q Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps The CGS states of each lane can be monitored using the CSYNC_STATE_P_LNx_XY bits of register CSYNC_STATE_LNx_XY . The definition of each state can be found in Table 30. 11.7.5.6 SYNC configuration The SYNC signal is the feedback signal that is sent to the transmitter device to ensure the JESD204B link synchronization. When all lanes are in CSYNC_INIT state a synchronization request is sent to the SYNC buffer that is linked to pins SYNC_OUTP and SYNC_OUTN (see Figure 2). The polarity of this buffer is controlled by bit SYNC_POL_XY of register SYNCOUT_MOD_XY . By default the sync_request is active low. The sync_request signal can be specified by bits SEL_SYNC and SYNC_INIT_LVL of register SYNCOUT_MOD_XY register. Bit SYNC_INIT_LVL_XY of register SYNCOUT_MOD_XY only specifies the state of the sync_request signal after resetting the CGS state machine (at start-up time or after device reset only). Fig 52. Code group synchronization Table 30. Code group synchronization state machine CSYNC_STATE_LNn[1:0] Name Definition 00 CSYNC_INIT looking for K28_5 (/K/) symbol 01 CSYNC_CHCK four consecutive K28_5 (/K/) symbols have been received 10 CSYNC_DATA code group synchronization achieved reset/start-up SYNC_INIT_LVL sync_request while receiving less than 4 consecutive VALID K28.5 symbols while receiving VALID symbols while receiving less than 4 consecutive VALID symbols or after receiving 3 INVALID symbols after receiving 4 consecutive VALID K28.5 symbols after receiving 4 consecutive VALID symbols after receiving 1 INVALID symbol after receiving 3 INVALID symbols CS_CHECK CS_INIT CS_DATA Table 31. Sync_request control SEL_SYNC[2:0] Description 000 sync_request active when state machine of one of the lanes is in CS_INIT mode 001 sync_request active when state machine of all lanes is in CS_INIT mode 010 sync_request active when state machine of lane 0 is in CS_INIT mode 011 sync_request active when state machine of lane 1 is in CS_INIT mode |
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