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DAC1658Q1G5NAGA Datasheet(HTML) 80 Page - Integrated Device Technology

Part No. DAC1658Q1G5NAGA
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1658Q1G5NAGA Datasheet(HTML) 80 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
80 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
LMF = 124
Sample assembly is based on the logical lanes definition when updating the L value .
11.7.5.10
Resynchronization over links
The DAC165xQ recognizes a K28.5 (/K/) symbols sequence coming over its lanes. This
identification allows resynchronization of the device if the RESYNC_OLINK_L_LNx_XY
bits of register REINIT_CTRL_XY are set correctly .
11.7.5.11 Symbols detection monitoring and error handling
The DLP decodes the 10-bit words to 8-bit words. The decoding table is specified in the
IEEE 802.3-2005 specification. During decoding, the disparity is calculated according to
the disparity rules mentioned in the same specification. The JESD204B specification also
defines the following definitions:
VALID:
The code group is found in the column of the 10b/8b decoding tables according to the
current running disparity.
DISPARITY ERROR:
The received code group exists in the 10b/8b decoding table, but is not found in the
correct column according to the current running disparity.
NOT-IN-TABLE (NIT) ERROR:
The received code group is not found in the 10b/8b decoding table of either disparity.
INVALID:
A code group that either shows a disparity error or that does not exist in the 10b/8b
decoding table.
The Not-In-Table error (NIT) and Disparity error (DISP) can be monitored using bits
DEC_NIT_ERR_P_LNx_XY and DEC_DISP_ERR_P_LNx_XY of the DEC_FLAGS_XY
register . Both are considered Invalid, but the DAC165xQ has some flexibility in this
definition. Using the NAD_ERR_CORR bit of the ERR_HNDLNG register either NIT errors
only or NIT errors and disparity errors can be set as INVALID. Moreover, the specified
invalid errors can also be totally ignored by setting the bit IGN_ERR_XY of the
ERR_HNDLNG register to logic 1 . This specific mode is designed for debug purposes
only, especially when sample error measurement needs to be executed.
The VALID/INVALID status of the decoded word can trigger the MUTE feature using bits
DATA_V_IQ_CFG_XY of the MUTE_CTRL_1_XY register .
The following comma symbols are detected during data transmission irrespective of the
running disparity:
/K/ = K28.5
/F/ = K28.7
/A/ = K28.3
/R/ = K28.0
/Q/ = K28.4
Their single detection is monitored in registers KOUT_FLAG_XY and K28_FLAG_XY (.


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