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DAC1658Q1G5NAGA Datasheet(HTML) 82 Page - Integrated Device Technology

Part No. DAC1658Q1G5NAGA
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1658Q1G5NAGA Datasheet(HTML) 82 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
82 of 101
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
When the counters are stopped, an interrupt can be activated .
This feature makes it possible to, for instance, analyze the occurrence of character
replacement or NIT errors.
11.7.6.2 Sample Error Rate (SER)
A sample error rate feature is implemented in the DAC165xQ to analyze the quality of the
transmission. Due to the 8b10b encoding, the analysis is done at sample level only and
not at bit level. The transmitter sends a constant data over the link and the DAC165xQ
compared this received value to the value specified in the SER_LVL_XY_LSB and
SER_LVL_XY_MSB registers . Enable the scrambling on both transmitter and receiver
side to add more random effect on the data. The SER_LVL_XY_MSB and
SER_LVL_XY_LSB are specifying a 16-bit value at the lane level, it means the device can
be considered as operating in one of two modes:
F = 2 mode:
The lane is receiving 16-bit data specified by SER_LVL_XY_MSB and
SER_LVL_XY_LSB.
F = 1 mode:
The lane is receiving alternately 8-bit data specified by SER_LVL_XY_MSB and
SER_LVL_XY_LSB.
The SER mode requires that the DAC is already synchronized (using CGS and ILA
sequence). The kick-off of the measurement is done by setting the SER_MOD_XY bit of
register SER_INTR_CTRL_XY . In this mode, the flags counters are used to count the
number of 16-bit samples that do not match the SER_LVL_XY value. This mode enables
the establishing of the sample error rate of each lane.
11.7.6.3 JTSPAT test
The Jitter Tolerance Scrambled PATtern (JTSPAT) is an 1180-bit pattern intended for
receiving jitter tolerance testing for scrambled systems. The JTSPAT test pattern consists
of two copies of JSPAT and an additional 18 characters intended to cause extreme late
and early phases in the CDR PLL followed by a sequence, which can cause an error
(i.e. an isolated bit following a long run). This pattern was developed to stress the receiver
within the boundary conditions established by scrambling.
Table 34.
HOLD_FLAG_CNT_EN_XY options
Default settings are shown highlighted.
HOLD_FLAG_CNT_EN_XY
Option
0
All counters are independent. Each counter continues its own
counting.
1
All counters are linked. When one counter reached the maximum
value and stops, all other counters stop as well.


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