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DAC1658Q1G5NAGA Datasheet(HTML) 98 Page - Integrated Device Technology

Part No. DAC1658Q1G5NAGA
Description  Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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DAC1658Q1G5NAGA Datasheet(HTML) 98 Page - Integrated Device Technology

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DAC1653Q/DAC1658Q
© IDT 2013. All rights reserved.
Advance data sheet
Rev. 1.03 — 13 May 2013
98 of 101
continued >>
Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
16. Tables
Table 1.
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Table 2.
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 3.
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4.
Thermal characteristics . . . . . . . . . . . . . . . . . . .8
Table 5.
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 6.
Specific characteristics . . . . . . . . . . . . . . . . . .12
Table 7.
Dynamic characteristics DAC165xQ1G50 . . . .15
Table 8.
Dynamic characteristics DAC165xQ1G25 . . . .17
Table 9.
Dynamic characteristics DAC16QxD1G . . . . .19
Table 10. LMF configuration if DAC165xQ configures in dual
JEDS204B links . . . . . . . . . . . . . . . . . . . . . . . .24
Table 11. Read mode or Write mode access description 28
Table 12. Double buffered registers . . . . . . . . . . . . . . . .29
Table 13. SPI timing characteristics . . . . . . . . . . . . . . . .31
Table 14. Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 15: Interpolation filter coefficients . . . . . . . . . . . . .34
Table 16. Complex modulator operation mode . . . . . . . .36
Table 17. Inversion filter coefficients . . . . . . . . . . . . . . . .38
Table 18. DAC transfer function . . . . . . . . . . . . . . . . . . .39
Table 19. Mute event categories . . . . . . . . . . . . . . . . . . .43
Table 20. Mute rate availability . . . . . . . . . . . . . . . . . . . .46
Table 21. Digital offset adjustment . . . . . . . . . . . . . . . . .47
Table 22. Level detector values . . . . . . . . . . . . . . . . . . . .48
Table 23. Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 24. WCLK_DIV selection . . . . . . . . . . . . . . . . . . . .51
Table 25. Interpolation and CDI modes . . . . . . . . . . . . . .52
Table 26. Relationship between various clocks . . . . . . . .57
Table 27. INTR_MOD settings . . . . . . . . . . . . . . . . . . . . .70
Table 28. Logical lanes versus L values . . . . . . . . . . . . .74
Table 29. Lane mapping between logical and physical lanes
regarding the L value . . . . . . . . . . . . . . . . . . . .75
Table 30. Code group synchronization state machine . . .77
Table 31. Sync_request control . . . . . . . . . . . . . . . . . . . .77
Table 32. Overview of generic parts of register addresses .
79
Table 33. Counter source . . . . . . . . . . . . . . . . . . . . . . . .81
Table 34. HOLD_FLAG_CNT_EN_XY options . . . . . . . .82
Table 35. Jitter tolerance scrambled pattern symbols
sequence[1] . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 36. Definition of IO_SEL registers . . . . . . . . . . . . .84
Table 37. Output signals for combination of indicators and
ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 38. Digital layer processing latency . . . . . . . . . . . .85
Table 39. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table 40. Revision history . . . . . . . . . . . . . . . . . . . . . . . .97


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