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DAC1658Q1G25NAGA Datasheet(PDF) 8 Page - Integrated Device Technology |
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DAC1658Q1G25NAGA Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 101 page DAC1653Q/DAC1658Q © IDT 2013. All rights reserved. Advance data sheet Rev. 1.03 — 13 May 2013 8 of 101 Integrated Device Technology DAC1653Q/DAC1658Q Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps 7. Limiting values 8. Thermal characteristics [1] In compliance with JEDEC test board; in free air with 64 thermal vias, class 5. [2] In free air with 64 thermal vias, class 5. Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDDA(out) analog output supply voltage DAC1658Q: 3.3 V 0.5 +4.6 V DAC1653Q: 2.5 V or 3.3 V 0.5 +4.6 V VDDD(1V2) digital supply voltage (1.2 V) 0.5 +1.5 V VDDA(1V2) analog supply voltage (1.2 V) 0.5 +1.5 V VI input voltage input pins referenced to GND 0.5 <tbd> V VO output voltage pins IOUTA_P, IOUTA_N, IOUTB_P, IOUTB_N, IOUTC_P, IOUTC_N, IOUTD_P, IOUTD_N; IO0; IO1; IO2; IO3; referenced to GND 0.5 +4.6 V VDDD(IO) I/O digital supply voltage pins SDO, SDIO,SCLK, SCS_N, RESET_N, JTAG, IO0, RF_ENABLE/IO1 0.5 2.1 V VDDD(SO) differential SYNC voltage pins SYNC_AB_P/N and SYNC_CD_P/N 0.5 2.1 V Tstg storage temperature 55 +150 C Tamb ambient temperature 40 +85 C Tj junction temperature 40 +125 C Table 4. Thermal characteristics Symbol Parameter Conditions Typ Unit JEDEC 4L board Rth(j-a) thermal resistance from junction to ambient [1] <tbd> K/W Rth(j-c) thermal resistance from junction to case [1] <tbd> K/W Application board Rth(j-a) thermal resistance from junction to ambient 6 layers [2] <tbd> K/W 8 layers [2] <tbd> K/W 12 layers [2] <tbd> K/W |
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